Commit Graph

125 Commits (4d594a663799f0b3b33f3dbd5284ca81476795d7)

Author SHA1 Message Date
Nabile Rahmani 4d594a6637 Turn DotN64 into a library, reference it and SDL2 for the desktop project. 2018-06-11 19:51:06 +02:00
Nabile Rahmani 1520e77849 Added SDL2. 2018-06-11 11:20:52 +02:00
Nabile Rahmani 5f868004b7 RCP: Reordered and shortened memory maps. 2018-06-10 17:46:20 +02:00
Nabile Rahmani 575f68c549 Debugger: surround register contents with brackets. 2018-06-10 17:33:54 +02:00
Nabile Rahmani 6550d7d327 More country codes. 2018-06-09 20:21:54 +02:00
Nabile Rahmani a13aa374d3 Instruction: FromOpCode => From. 2018-06-09 18:56:57 +02:00
Nabile Rahmani 9762d813ba Ensure GPR[0] is zero. 2018-06-09 18:35:33 +02:00
Nabile Rahmani 40d0944418 SysAD: "value" => "data". 2018-06-09 18:31:15 +02:00
Nabile Rahmani a7972ebc0a Replaced CP0 register index abstract property by a readonly field. 2018-06-09 18:17:06 +02:00
Nabile Rahmani c15c1d0b18 Fixed exceptions not setting the correct branch delay value. 2018-06-09 18:10:39 +02:00
Nabile Rahmani eb41337dce CPU: refactored control flow and load/store methods, added new ops. 2018-06-09 17:40:52 +02:00
Nabile Rahmani dca7725258 Refactored CP0 stuff. 2018-06-05 20:44:13 +02:00
Nabile Rahmani 05cf22619a Mapping entry formatting. 2018-06-05 17:32:59 +02:00
Nabile Rahmani 17e13ce564 FPU:
- Removed duplicate condition signal variable.
- Check for the unimplemented operation flag.
2018-06-05 17:19:02 +02:00
Nabile Rahmani be7b7c9827 Refactored flags and renamed registers. 2018-05-11 16:16:54 +02:00
Nabile Rahmani ecab40e39e Added ops. 2018-01-24 17:21:08 +01:00
Nabile Rahmani a60f8a7dbf SLT comparison is *signed*, duh. 2018-01-24 16:31:36 +01:00
Nabile Rahmani 6caa80fb9a More ops. 2018-01-24 03:06:39 +01:00
Nabile Rahmani 1800179515 - Added the FPU.
- Added an exception handler for the FPU.
- Added constants for cartridges and fixed header properties.
- PIF HLE determines the console region for the saved register that's used by the OS.
- The disassembler shows CP1 opcodes.
2018-01-23 18:46:12 +01:00
Nabile Rahmani 9910f7ab0b Added license. 2018-01-17 18:08:30 +01:00
Nabile Rahmani 8e076ff0ae Moved CP0.OpCode enum. 2018-01-17 17:30:01 +01:00
Nabile Rahmani 4ee50a1f7f Coprocessor, debugger, and exception stuff.
* VR4300.SystemControlUnit.cs: Implemented coprocessor operations.

* VR4300.ExceptionProcessing.cs: More exceptions.

* VR4300.Exceptions.cs: Support coprocessor ops.

* DotN64.csproj:
* VR4300.ICoprocessor.cs:

* VR4300.Instruction.cs: Implemented IEquatable to avoid boxing in
  dictionary key comparisons.
Added COPz for coprocessor ops.

* VR4300.OpCode.cs: Proper coprocessor ops.

* VR4300.cs: Added coprocessor unit support.

* Debugger.InstructionFormat.cs: (Slightly) take into account
  coprocessor ops.

* Debugger.cs: Using an instruction cursor to avoid confusion.
Fixed a case where the debugger would run a cycle despite exiting it.
Coprocessor ops aren't properly disassembled.
2018-01-17 10:34:02 +01:00
Nabile Rahmani da3a886d71 Move IP to a structure. 2018-01-02 15:34:22 +01:00
Nabile Rahmani 158f01ccf9 Exception processing, interrupts, registers. 2018-01-01 18:01:59 +01:00
Nabile Rahmani 08853d495f The CPU only supports 32-bit physical addresses.
No point in keeping the result of translated addresses 64-bit.
2017-12-20 01:50:44 +01:00
Nabile Rahmani cc81d9d21d As the external agent, the RCP should define its memory maps. 2017-12-20 01:20:12 +01:00
Nabile Rahmani 71904ce63f PI. 2017-12-19 20:24:14 +01:00
Nabile Rahmani b2ea1dbdb6 Changed casing to follow naming conventions. 2017-12-18 09:10:07 +01:00
Nabile Rahmani 17dbe71cef * VR4300.Exceptions.cs: Added a custom exception.
* VR4300.cs: Fixed SLLV/SRLV not downcasting a register source.

* Debugger.InstructionFormat.cs: Added some more formatting
  exceptions.

* Program.cs:
* Cartridge.cs:
* DotN64.csproj:
* RDRAM.cs:
* PeripheralInterface.cs:
* RDRAM.ConfigIndex.cs:
* RDRAM.ConfigRegister.cs:
* PeripheralInterface.CIC.cs:
* PeripheralInterface.CICStatus.cs:
* PeripheralInterface.DeviceState.cs:
* RealityCoprocessor.RDRAMInterface.cs:
* RealityCoprocessor.PeripheralInterface.cs:

* Nintendo64.cs: Added peripherals and rewiring.

* RealityCoprocessor.PeripheralInterface.StatusRegister.cs: Moved
  write register constants to an enum, too.

* BitHelper.cs: Better method signatures.
2017-12-18 08:50:25 +01:00
Nabile Rahmani 23b06e69b5 Huge changes (too lazy to separate).
* VR4300.SystemControlUnit.StatusRegister.cs: Removed unneeded
  value.

* VR4300.SystemControlUnit.cs: Renamed method.

* VR4300.Instruction.cs: Refactored instruction contents. Now
  individual parts can be written to as well.
It is also possible to strip an instruction to its bare opcode
  identifier, or even create one from a specified opcode, so this can
  be used as a key in a dictionary of operations.
A basic ToString implementation displays the opcode of the
  instruction.

* VR4300.OpCode.cs:
* VR4300.RegImmOpCode.cs:
* VR4300.SpecialOpCode.cs: Added opcodes.

* VR4300.cs: Unified operations into a single dictionary thanks to the
  instruction refactoring.
Added ops: JAL, SLTI, XORI, BLEZL, SB, LBU, SLT, BGEZL.

* Debugger.Command.cs: Basic display of what the command is about.

* Debugger.InstructionFormat.cs: First pass of the formatter.

* Debugger.cs: Proper disassembly of instructions. Stepping also
  displays the contents of registers.
~Infinite~ count argument for stepping/disassembling.
Refactored instruction fetch into using the CPU's SysAD bus (no need
  to manually access the N64's memory maps).

* DotN64.csproj:
* RealityCoprocessor.SignalProcessor.StatusRegister.cs:
* RealityCoprocessor.DisplayProcessor.StatusRegister.cs:
* RealityCoprocessor.RDRAMInterface.RDRAMConfigIndex.cs:
* RealityCoprocessor.RDRAMInterface.RDRAMConfigRegister.cs:

* MappingEntryExtensions.cs: Saves some typing.

* BitHelper.cs: Reusable methods.

* Nintendo64.cs: More memory maps.

* Program.cs: Minor changes.

* RealityCoprocessor.Interface.cs:
* RealityCoprocessor.AudioInterface.cs:
* RealityCoprocessor.VideoInterface.cs:
* RealityCoprocessor.SerialInterface.cs: Simplified mapping accesses.

* RealityCoprocessor.DisplayProcessor.cs: Added an actual register.
Simplified mapping accesses.

* RealityCoprocessor.MIPSInterface.cs: Added dummy version register
  read.
Simplified mapping accesses.

* RealityCoprocessor.PeripheralInterface.cs: Basic DMA.
Simplified mapping accesses.

* RealityCoprocessor.RDRAMInterface.cs: Removed constants that get set
  in the boot process.
Added RDRAM registers.
Simplified mapping accesses.

* RealityCoprocessor.SignalProcessor.cs: Better types for existing
  registers and handle status writes.
Simplified mapping accesses.
2017-12-11 15:04:53 +01:00
Nabile Rahmani 8905d75136 Updated boot ROM HLE:
Removed temporary and cartridge-specific register values.
2017-11-27 08:28:00 +01:00
Nabile Rahmani a6ae17a345 Use SysAD pins instead of passing maps. 2017-11-21 12:59:59 +01:00
Nabile Rahmani f20f931b12 Aesthetic. 2017-11-16 22:43:43 +01:00
Nabile Rahmani 12f287ea12 Make delay slot accessible for the debugger. 2017-11-16 11:41:46 +01:00
Nabile Rahmani 449b6ebd0c A debugger appeared. 2017-11-16 08:33:04 +01:00
Nabile Rahmani 66e5efff59 Moved members in their respective place. 2017-11-04 17:59:34 +01:00
Nabile Rahmani c323daf588 Moved the CPU in its own folder. 2017-11-04 16:28:09 +01:00
Nabile Rahmani ea629a6b16 Moved RCP interfaces inside itself. 2017-11-04 15:24:26 +01:00
Nabile Rahmani 467ea2a07d Proper CPU reset. 2017-11-04 13:43:15 +01:00
Nabile Rahmani 35932316c4 Renames. 2017-11-04 12:14:51 +01:00
Nabile Rahmani 59fd18ce2c Unified interfaces. 2017-10-31 12:50:00 +01:00
Nabile Rahmani 20c2b5ab78 PI registers. 2017-10-30 22:09:25 +01:00
Nabile Rahmani 2ebfa53387 - Fake CACHE.
- Pretty print maps.
- Main memory get.
2017-10-30 21:46:09 +01:00
Nabile Rahmani dbe5cc6559 ... Aren't they more cute as enumerations ? 2017-10-30 19:56:49 +01:00
Nabile Rahmani d5efc12872 Added register and defaults from MAME. 2017-10-30 14:06:06 +01:00
Nabile Rahmani a605598241 More registers. 2017-10-30 12:55:01 +01:00
Nabile Rahmani d7e97d9b46 Changed target framework. 2017-10-30 10:08:44 +01:00
Nabile Rahmani 9da7b68741 - Reduced memory allocation and CPU usage by not using LINQ, foreach in hot paths and unsafe writes instead of array copies.
- 64-bit addressing in mapping entries instead of down-casting.
- Fixed cartridge field length.
- Adjusted ops.
2017-10-30 10:05:09 +01:00
Nabile Rahmani f938e58c2e Name change. 2017-10-09 08:21:31 +02:00
Nabile Rahmani 3eebb0a9ad Updated PIF HLE. 2017-10-08 03:09:48 +02:00