* VR4300.Exceptions.cs: Added a custom exception.
* VR4300.cs: Fixed SLLV/SRLV not downcasting a register source. * Debugger.InstructionFormat.cs: Added some more formatting exceptions. * Program.cs: * Cartridge.cs: * DotN64.csproj: * RDRAM.cs: * PeripheralInterface.cs: * RDRAM.ConfigIndex.cs: * RDRAM.ConfigRegister.cs: * PeripheralInterface.CIC.cs: * PeripheralInterface.CICStatus.cs: * PeripheralInterface.DeviceState.cs: * RealityCoprocessor.RDRAMInterface.cs: * RealityCoprocessor.PeripheralInterface.cs: * Nintendo64.cs: Added peripherals and rewiring. * RealityCoprocessor.PeripheralInterface.StatusRegister.cs: Moved write register constants to an enum, too. * BitHelper.cs: Better method signatures.master
parent
23b06e69b5
commit
17dbe71cef
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@ -0,0 +1,28 @@
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using System;
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namespace DotN64.CPU
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{
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public partial class VR4300
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{
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public class UnimplementedOperationException : Exception
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{
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#region Properties
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public Instruction Instruction { get; }
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#endregion
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#region Constructors
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public UnimplementedOperationException(Instruction instruction)
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: base($"Unimplemented opcode ({GetOpCodeType(instruction).Name} {FormatOpCodeBits(instruction)}) from instruction 0x{(uint)instruction:X8}.")
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{
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Instruction = instruction;
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}
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#endregion
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#region Methods
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private static Type GetOpCodeType(Instruction instruction) => instruction.Special?.GetType() ?? instruction.RegImm?.GetType() ?? instruction.OP.GetType();
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private static string FormatOpCodeBits(Instruction instruction) => "0b" + Convert.ToString((byte?)instruction.Special ?? (byte?)instruction.RegImm ?? (byte)instruction.OP, 2);
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#endregion
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}
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}
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}
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@ -94,7 +94,7 @@ namespace DotN64.CPU
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[Instruction.FromOpCode(OpCode.MTC0)] = i => CP0.Registers[i.RD] = GPR[i.RT],
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[Instruction.FromOpCode(OpCode.ORI)] = i => GPR[i.RT] = GPR[i.RS] | i.Immediate,
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[Instruction.FromOpCode(OpCode.LW)] = i => GPR[i.RT] = (ulong)(int)ReadWord((ulong)(short)i.Immediate + GPR[i.RS]),
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[Instruction.FromOpCode(OpCode.ANDI)] = i => GPR[i.RT] = (ulong)(i.Immediate & (ushort)GPR[i.RS]),
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[Instruction.FromOpCode(OpCode.ANDI)] = i => GPR[i.RT] = i.Immediate & GPR[i.RS],
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[Instruction.FromOpCode(OpCode.BEQL)] = i => BranchLikely(i, (rs, rt) => rs == rt),
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[Instruction.FromOpCode(OpCode.ADDIU)] = i => GPR[i.RT] = (ulong)(int)(GPR[i.RS] + (ulong)(short)i.Immediate),
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[Instruction.FromOpCode(OpCode.SW)] = i => WriteWord((ulong)(short)i.Immediate + GPR[i.RS], (uint)GPR[i.RT]),
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@ -140,8 +140,8 @@ namespace DotN64.CPU
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[Instruction.FromOpCode(SpecialOpCode.MFHI)] = i => GPR[i.RD] = HI,
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[Instruction.FromOpCode(SpecialOpCode.ADDU)] = i => GPR[i.RD] = (ulong)((int)GPR[i.RS] + (int)GPR[i.RT]),
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[Instruction.FromOpCode(SpecialOpCode.SLTU)] = i => GPR[i.RD] = (ulong)(GPR[i.RS] < GPR[i.RT] ? 1 : 0),
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[Instruction.FromOpCode(SpecialOpCode.SLLV)] = i => GPR[i.RD] = (ulong)(int)(GPR[i.RT] << (int)(GPR[i.RS] & ((1 << 5) - 1))),
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[Instruction.FromOpCode(SpecialOpCode.SRLV)] = i => GPR[i.RD] = (ulong)(int)(GPR[i.RT] >> (int)(GPR[i.RS] & ((1 << 5) - 1))),
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[Instruction.FromOpCode(SpecialOpCode.SLLV)] = i => GPR[i.RD] = (ulong)(int)((uint)GPR[i.RT] << (int)(GPR[i.RS] & ((1 << 5) - 1))),
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[Instruction.FromOpCode(SpecialOpCode.SRLV)] = i => GPR[i.RD] = (ulong)(int)((uint)GPR[i.RT] >> (int)(GPR[i.RS] & ((1 << 5) - 1))),
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[Instruction.FromOpCode(SpecialOpCode.AND)] = i => GPR[i.RD] = GPR[i.RS] & GPR[i.RT],
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[Instruction.FromOpCode(SpecialOpCode.SLT)] = i => GPR[i.RD] = GPR[i.RS] < GPR[i.RT] ? (ulong)1 : 0,
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[Instruction.FromOpCode(RegImmOpCode.BGEZAL)] = i => Branch(i, (rs, rt) => rs >= 0, true),
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@ -179,7 +179,7 @@ namespace DotN64.CPU
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if (operations.TryGetValue(instruction.ToOpCode(), out var operation))
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operation(instruction);
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else
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throw new Exception($"Unknown opcode from instruction 0x{(uint)instruction:X8}.");
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throw new UnimplementedOperationException(instruction);
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}
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public void Step()
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@ -5,21 +5,23 @@ using System.Text;
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namespace DotN64
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{
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using Helpers;
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public class Cartridge
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{
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#region Properties
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public byte[] ROM { get; set; }
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public uint ClockRate => (uint)IPAddress.NetworkToHostOrder(BitConverter.ToInt32(ROM, 0x04));
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public uint ClockRate => BitHelper.FromBigEndian(BitConverter.ToUInt32(ROM, 0x04));
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public uint BootAddressOffset => (uint)IPAddress.NetworkToHostOrder(BitConverter.ToInt32(ROM, 0x08));
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public uint BootAddressOffset => BitHelper.FromBigEndian(BitConverter.ToUInt32(ROM, 0x08));
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public uint ReleaseOffset => (uint)IPAddress.NetworkToHostOrder(BitConverter.ToInt32(ROM, 0x0C));
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public uint ReleaseOffset => BitHelper.FromBigEndian(BitConverter.ToUInt32(ROM, 0x0C));
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public uint[] CRC => new[]
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{
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(uint)IPAddress.NetworkToHostOrder(BitConverter.ToInt32(ROM, 0x10)),
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(uint)IPAddress.NetworkToHostOrder(BitConverter.ToInt32(ROM, 0x14))
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BitHelper.FromBigEndian(BitConverter.ToUInt32(ROM, 0x10)),
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BitHelper.FromBigEndian(BitConverter.ToUInt32(ROM, 0x14))
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};
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public string ImageName => Encoding.ASCII.GetString(ROM, 0x20, 0x34 - 0x20);
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@ -60,9 +60,17 @@
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{
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case VR4300.SpecialOpCode.JR:
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return Format(instruction, FormatRegister(instruction.RS, cpu));
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case VR4300.SpecialOpCode.MFHI:
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case VR4300.SpecialOpCode.MFLO:
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return Format(instruction, FormatRegister(instruction.RD, cpu));
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case VR4300.SpecialOpCode.MULTU:
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return Format(instruction, FormatRegister(instruction.RS, cpu), FormatRegister(instruction.RT, cpu));
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case VR4300.SpecialOpCode.SLLV:
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case VR4300.SpecialOpCode.SRLV:
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return Format(instruction, FormatRegister(instruction.RD, cpu), FormatRegister(instruction.RT, cpu), FormatRegister(instruction.RS, cpu));
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case VR4300.SpecialOpCode.SLL:
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case VR4300.SpecialOpCode.SRL:
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return Format(instruction, FormatRegister(instruction.RD, cpu), FormatRegister(instruction.RT, cpu), (sbyte)instruction.SA);
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}
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switch (instruction.OP)
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@ -43,7 +43,6 @@
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<Compile Include="RCP\MI\RealityCoprocessor.MIPSInterface.cs" />
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<Compile Include="RCP\MI\RealityCoprocessor.MIPSInterface.InitModeRegister.cs" />
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<Compile Include="RCP\PI\RealityCoprocessor.PeripheralInterface.cs" />
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<Compile Include="RCP\PI\RealityCoprocessor.PeripheralInterface.CICStatus.cs" />
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<Compile Include="RCP\PI\RealityCoprocessor.PeripheralInterface.Domain.cs" />
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<Compile Include="RCP\PI\RealityCoprocessor.PeripheralInterface.StatusRegister.cs" />
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<Compile Include="RCP\RI\RealityCoprocessor.RDRAMInterface.cs" />
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@ -72,8 +71,14 @@
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<Compile Include="Helpers\BitHelper.cs" />
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<Compile Include="RCP\DP\RealityCoprocessor.DisplayProcessor.StatusRegister.cs" />
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<Compile Include="RCP\SP\RealityCoprocessor.SignalProcessor.StatusRegister.cs" />
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<Compile Include="RCP\RI\RealityCoprocessor.RDRAMInterface.RDRAMConfigRegister.cs" />
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<Compile Include="RCP\RI\RealityCoprocessor.RDRAMInterface.RDRAMConfigIndex.cs" />
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<Compile Include="CPU\VR4300\VR4300.Exceptions.cs" />
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<Compile Include="PIF\PeripheralInterface.cs" />
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<Compile Include="PIF\PeripheralInterface.CICStatus.cs" />
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<Compile Include="PIF\PeripheralInterface.DeviceState.cs" />
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<Compile Include="RDRAM\RDRAM.cs" />
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<Compile Include="RDRAM\RDRAM.ConfigIndex.cs" />
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<Compile Include="RDRAM\RDRAM.ConfigRegister.cs" />
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<Compile Include="PIF\PeripheralInterface.CIC.cs" />
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</ItemGroup>
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<ItemGroup>
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<Folder Include="CPU\" />
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@ -91,6 +96,8 @@
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<Folder Include="CPU\VR4300\CP0\" />
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<Folder Include="Diagnostics\" />
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<Folder Include="Helpers\" />
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<Folder Include="PIF\" />
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<Folder Include="RDRAM\" />
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</ItemGroup>
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<Import Project="$(MSBuildBinPath)\Microsoft.CSharp.targets" />
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</Project>
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@ -1,4 +1,5 @@
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using System.Runtime.CompilerServices;
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using System.Net;
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using System.Runtime.CompilerServices;
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namespace DotN64.Helpers
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{
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@ -25,6 +26,7 @@ namespace DotN64.Helpers
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data |= (value & size) << shift;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public static unsafe void Write(byte[] data, int index, uint value)
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{
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fixed (byte* pointer = &data[index])
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*(uint*)pointer = value;
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}
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public static uint FromBigEndian(uint value) => (uint)IPAddress.NetworkToHostOrder((int)value);
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public static uint ToBigEndian(uint value) => (uint)IPAddress.HostToNetworkOrder((int)value);
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#endregion
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}
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}
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@ -15,7 +15,9 @@ namespace DotN64
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public RealityCoprocessor RCP { get; }
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public byte[] RAM { get; } = new byte[0x00400000]; // The base system has 4 MB of RAM installed.
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public RDRAM RAM { get; } = new RDRAM(new byte[0x00400000]); // The base system has 4 MB of RAM installed.
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public PeripheralInterface PIF { get; }
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public Cartridge Cartridge { get; set; }
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#endregion
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public Nintendo64()
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{
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RCP = new RealityCoprocessor(this);
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PIF = new PeripheralInterface(this);
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MemoryMaps = new[]
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{
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new MappingEntry(0x1FC00000, 0x1FC007BF, false) // PIF Boot ROM.
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{
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Read = RCP.PI.MemoryMaps.ReadWord,
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Write = RCP.PI.MemoryMaps.WriteWord
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Read = PIF.MemoryMaps.ReadWord,
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Write = PIF.MemoryMaps.WriteWord
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},
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new MappingEntry(0x1FC007C0, 0x1FC007FF, false) // PIF (JoyChannel) RAM.
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{
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Read = RCP.PI.MemoryMaps.ReadWord,
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Write = RCP.PI.MemoryMaps.WriteWord
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Read = PIF.MemoryMaps.ReadWord,
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Write = PIF.MemoryMaps.WriteWord
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},
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new MappingEntry(0x04600000, 0x046FFFFF, false) // Peripheral interface (PI) registers.
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{
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@ -82,13 +85,13 @@ namespace DotN64
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},
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new MappingEntry(0x00000000, 0x03EFFFFF, false) // RDRAM memory.
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{
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Read = RCP.RI.MemoryMaps.ReadWord,
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Write = RCP.RI.MemoryMaps.WriteWord
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Read = RAM.MemoryMaps.ReadWord,
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Write = RAM.MemoryMaps.WriteWord
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},
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new MappingEntry(0x03F00000, 0x03FFFFFF, false) // RDRAM registers.
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{
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Read = RCP.RI.MemoryMaps.ReadWord,
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Write = RCP.RI.MemoryMaps.WriteWord
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Read = RAM.MemoryMaps.ReadWord,
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Write = RAM.MemoryMaps.WriteWord
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}
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};
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CPU = new VR4300
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@ -104,9 +107,7 @@ namespace DotN64
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public void PowerOn()
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{
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CPU.Reset();
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if (RCP.PI.BootROM == null)
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RCP.PI.EmulateBootROM();
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PIF.Reset();
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}
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public void Run()
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@ -0,0 +1,62 @@
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namespace DotN64
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{
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public partial class PeripheralInterface
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{
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public static class CIC
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{
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#region Methods
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private static uint ComputeCRC32(byte[] data, int offset, int length)
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{
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var table = new uint[256];
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uint c;
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for (uint i = 0; i < table.Length; i++)
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{
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c = i;
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for (uint j = 0; j < 8; j++)
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{
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if ((c & 1) != 0)
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c = 0xEDB88320 ^ (c >> 1);
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else
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c >>= 1;
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}
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table[i] = c;
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}
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c = 0 ^ 0xFFFFFFFF;
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for (int i = 0; i < length; i++)
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{
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c = table[(c ^ (data[offset + i])) & 0xFF] ^ (c >> 8);
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}
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return c ^ 0xFFFFFFFF;
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}
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public static uint GetSeed(byte[] data, int offset = 0x40, int length = 0x1000 - 0x40)
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{
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switch (ComputeCRC32(data, offset, length))
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{
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case 0x6170A4A1: // NUS-6101.
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case 0x009E9EA3: // NUS-7102.
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return 0x00043F3F;
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case 0x90BB6CB5: // NUS-6102.
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return 0x00003F3F;
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case 0x0B050EE0: // NUS-6103.
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return 0x0000783F;
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case 0x98BC2C86: // NUS-6105.
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return 0x0000913F;
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case 0xACC8580A: // NUS-6106.
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return 0x0000853F;
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case 0x0E018159: // NUS-8303.
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return 0x0000DD00;
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default:
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return 0;
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}
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}
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#endregion
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}
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}
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}
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@ -0,0 +1,22 @@
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namespace DotN64
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{
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public partial class PeripheralInterface
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{
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private enum CICStatus : byte
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{
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/// <summary>
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/// The boot ROM copies the cartridge's bootstrap code [0x40, 0x1000[ into the RSP's DMEM while computing the CIC algorithm on the data.
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/// When done, it stores the result in the PIF RAM at [48, 56[.
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/// </summary>
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Computing = 16,
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/// <summary>
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/// The CPU waits for the PIF CPU to validate that the cartridge's CIC computed the same result stored in the PIF RAM.
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/// </summary>
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Waiting = 48,
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/// <summary>
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/// The CIC check matched, continue booting.
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/// </summary>
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OK = 128
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}
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}
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}
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using System.Collections.Specialized;
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namespace DotN64
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{
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public partial class PeripheralInterface
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{
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private struct DeviceState
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{
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#region Fields
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private BitVector32 bits;
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private static readonly BitVector32.Section ipl2SeedSection = BitVector32.CreateSection(0xFF),
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ipl3SeedSection = BitVector32.CreateSection(0xFF, ipl2SeedSection),
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resetSection = BitVector32.CreateSection(0x02, ipl3SeedSection),
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versionSection = BitVector32.CreateSection(0x02, resetSection),
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romSection = BitVector32.CreateSection(0x04, versionSection);
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#endregion
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#region Properties
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public byte IPL2Seed
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{
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get => (byte)bits[ipl2SeedSection];
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set => bits[ipl2SeedSection] = value;
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}
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public byte IPL3Seed
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{
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get => (byte)bits[ipl3SeedSection];
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set => bits[ipl3SeedSection] = value;
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}
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public ResetType Reset
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{
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get => (ResetType)bits[resetSection];
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set => bits[resetSection] = (byte)value;
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}
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public byte Version
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{
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get => (byte)bits[versionSection];
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set => bits[versionSection] = value;
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}
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public ROMType ROM
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{
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get => (ROMType)bits[romSection];
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set => bits[romSection] = (byte)value;
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}
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#endregion
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#region Operators
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public static implicit operator DeviceState(uint data) => new DeviceState { bits = new BitVector32((int)data) };
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public static implicit operator uint(DeviceState state) => (uint)state.bits.Data;
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#endregion
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#region Enumerations
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public enum ResetType : byte
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{
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ColdReset = 0,
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NMI = 1
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}
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public enum ROMType : byte
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{
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Cartridge = 0,
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DiskDrive = 1
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}
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#endregion
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}
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}
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}
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|
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@ -0,0 +1,134 @@
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using System;
|
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using System.Collections.Generic;
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namespace DotN64
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{
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using CPU;
|
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using Extensions;
|
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using Helpers;
|
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|
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public partial class PeripheralInterface
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{
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#region Fields
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private readonly Nintendo64 nintendo64;
|
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private const byte CICStatusOffset = 0x3C, DeviceStateOffset = 0x24;
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#endregion
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#region Properties
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public IReadOnlyList<MappingEntry> MemoryMaps { get; }
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public byte[] BootROM { get; set; }
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||||
|
||||
public byte[] RAM { get; } = new byte[64];
|
||||
|
||||
private DeviceState DeviceStateFlags
|
||||
{
|
||||
get => BitConverter.ToUInt32(RAM, DeviceStateOffset);
|
||||
set => BitHelper.Write(RAM, DeviceStateOffset, value);
|
||||
}
|
||||
#endregion
|
||||
|
||||
#region Constructors
|
||||
public PeripheralInterface(Nintendo64 nintendo64)
|
||||
{
|
||||
this.nintendo64 = nintendo64;
|
||||
MemoryMaps = new[]
|
||||
{
|
||||
new MappingEntry(0x1FC00000, 0x1FC007BF) // PIF Boot ROM.
|
||||
{
|
||||
Read = o => BitHelper.FromBigEndian(BitConverter.ToUInt32(BootROM, (int)o))
|
||||
},
|
||||
new MappingEntry(0x1FC007C0, 0x1FC007FF) // PIF (JoyChannel) RAM.
|
||||
{
|
||||
Read = o => BitConverter.ToUInt32(RAM, (int)o),
|
||||
Write = (o, v) =>
|
||||
{
|
||||
BitHelper.Write(RAM, (int)o, v);
|
||||
OnRAMWritten((int)o);
|
||||
}
|
||||
}
|
||||
};
|
||||
}
|
||||
#endregion
|
||||
|
||||
#region Methods
|
||||
/// <summary>
|
||||
/// Called when a word is written at a specified index in the RAM.
|
||||
/// Handles actions sent through memory writes.
|
||||
/// </summary>
|
||||
private void OnRAMWritten(int index)
|
||||
{
|
||||
switch (index)
|
||||
{
|
||||
case CICStatusOffset:
|
||||
if (RAM[index] == (byte)CICStatus.Waiting) // The boot ROM waits for the PIF's CIC check to be OK.
|
||||
RAM[index] = (byte)CICStatus.OK; // We tell it it's OK by having the loaded word that gets ANDI'd match the immediate value 128, storing non-zero which allows us to exit the BEQL loop.
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
private void EmulateBootROM()
|
||||
{
|
||||
// Replicating the memory writes to properly initialise the subsystems.
|
||||
var writes = new uint[,]
|
||||
{
|
||||
{ 0x4040010, 0xA },
|
||||
{ 0x4600010, 0x3 },
|
||||
{ 0x440000C, 0x3FF },
|
||||
{ 0x4400024, 0x0 },
|
||||
{ 0x4400010, 0x0 },
|
||||
{ 0x4500000, 0x0 },
|
||||
{ 0x4500004, 0x0 },
|
||||
{ 0x4600014, 0x40 }, // These four are likely cartridge-specific (PI domain 1 values).
|
||||
{ 0x4600018, 0xFF803712 },
|
||||
{ 0x460001C, 0xFFFF8037 },
|
||||
{ 0x4600020, 0xFFFFF803 },
|
||||
// Omitted the CIC results.
|
||||
{ 0x1FC007FC, 0xC0 }
|
||||
};
|
||||
|
||||
for (int i = 0; i < writes.GetLength(0); i++)
|
||||
{
|
||||
nintendo64.MemoryMaps.WriteWord(writes[i, 0], writes[i, 1]);
|
||||
}
|
||||
|
||||
if (DeviceStateFlags.ROM == DeviceState.ROMType.Cartridge && nintendo64.Cartridge != null)
|
||||
{
|
||||
for (int i = 0x40; i < 0x1000; i += sizeof(uint)) // Copying the bootstrap code from the cartridge to the RSP's DMEM.
|
||||
{
|
||||
nintendo64.MemoryMaps.WriteWord((ulong)(0x04000000 + i), BitHelper.FromBigEndian(BitConverter.ToUInt32(nintendo64.Cartridge.ROM, i)));
|
||||
}
|
||||
}
|
||||
|
||||
nintendo64.CPU.GPR[(int)VR4300.GPRIndex.s3] = (ulong)DeviceStateFlags.ROM;
|
||||
// TODO: $s4 is the video mode (0 being PAL settings). This value is hard-coded into regional boot ROMs.
|
||||
nintendo64.CPU.GPR[(int)VR4300.GPRIndex.s5] = (ulong)DeviceStateFlags.Reset;
|
||||
nintendo64.CPU.GPR[(int)VR4300.GPRIndex.s6] = DeviceStateFlags.IPL3Seed;
|
||||
nintendo64.CPU.GPR[(int)VR4300.GPRIndex.s7] = DeviceStateFlags.Version;
|
||||
|
||||
// Restoring CPU state.
|
||||
nintendo64.CPU.CP0.Registers[12] = 0x34000000;
|
||||
nintendo64.CPU.CP0.Registers[16] = 0x6E463;
|
||||
nintendo64.CPU.GPR[6] = 0xFFFFFFFFA4001F0C;
|
||||
nintendo64.CPU.GPR[7] = 0xFFFFFFFFA4001F08;
|
||||
nintendo64.CPU.GPR[8] = 0xC0;
|
||||
nintendo64.CPU.GPR[10] = 0x40;
|
||||
nintendo64.CPU.GPR[11] = 0xFFFFFFFFA4000040;
|
||||
nintendo64.CPU.GPR[20] = 0x1;
|
||||
nintendo64.CPU.GPR[29] = 0xFFFFFFFFA4001FF0;
|
||||
nintendo64.CPU.GPR[31] = 0xFFFFFFFFA4001550;
|
||||
nintendo64.CPU.PC = 0xFFFFFFFFA4000040;
|
||||
}
|
||||
|
||||
public void Reset()
|
||||
{
|
||||
if (nintendo64.Cartridge?.ROM.Length >= 0x1000)
|
||||
DeviceStateFlags = CIC.GetSeed(nintendo64.Cartridge.ROM);
|
||||
|
||||
if (BootROM == null)
|
||||
EmulateBootROM();
|
||||
}
|
||||
#endregion
|
||||
}
|
||||
}
|
||||
|
|
@ -18,7 +18,7 @@ namespace DotN64
|
|||
switch (arg)
|
||||
{
|
||||
case "--pif-rom":
|
||||
nintendo64.RCP.PI.BootROM = File.ReadAllBytes(args[++i]);
|
||||
nintendo64.PIF.BootROM = File.ReadAllBytes(args[++i]);
|
||||
break;
|
||||
case "--debug":
|
||||
case "-d":
|
||||
|
|
|
|||
|
|
@ -1,25 +0,0 @@
|
|||
namespace DotN64.RCP
|
||||
{
|
||||
public partial class RealityCoprocessor
|
||||
{
|
||||
public partial class PeripheralInterface
|
||||
{
|
||||
private enum CICStatus : byte
|
||||
{
|
||||
/// <summary>
|
||||
/// The boot ROM copies the cartridge's bootstrap code [0x40, 0x1000[ into the RSP's DMEM while computing the CIC algorithm on the data.
|
||||
/// When done, it stores the result in the PIF RAM at [48, 56[.
|
||||
/// </summary>
|
||||
Computing = 16,
|
||||
/// <summary>
|
||||
/// The CPU waits for the PIF CPU to validate that the cartridge's CIC computed the same result stored in the PIF RAM.
|
||||
/// </summary>
|
||||
Waiting = 48,
|
||||
/// <summary>
|
||||
/// The CIC check matched, continue booting.
|
||||
/// </summary>
|
||||
OK = 128
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,16 +1,25 @@
|
|||
namespace DotN64.RCP
|
||||
using System;
|
||||
|
||||
namespace DotN64.RCP
|
||||
{
|
||||
public partial class RealityCoprocessor
|
||||
{
|
||||
public partial class PeripheralInterface
|
||||
{
|
||||
[System.Flags]
|
||||
[Flags]
|
||||
public enum StatusRegister
|
||||
{
|
||||
DMABusy = 1 << 0,
|
||||
IOBusy = 1 << 1,
|
||||
Error = 1 << 2
|
||||
}
|
||||
|
||||
[Flags]
|
||||
private enum WriteStatusRegister : byte
|
||||
{
|
||||
ResetController = 1 << 0,
|
||||
ClearInterrupt = 1 << 1
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,4 @@
|
|||
using System;
|
||||
using System.Net;
|
||||
|
||||
namespace DotN64.RCP
|
||||
{
|
||||
|
|
@ -10,18 +9,9 @@ namespace DotN64.RCP
|
|||
{
|
||||
public partial class PeripheralInterface : Interface
|
||||
{
|
||||
#region Fields
|
||||
private const byte CICStatusOffset = 60;
|
||||
private const byte ResetControllerStatus = 1 << 0, ClearInterruptStatus = 1 << 1;
|
||||
#endregion
|
||||
|
||||
#region Properties
|
||||
public StatusRegister Status { get; set; }
|
||||
|
||||
public byte[] BootROM { get; set; }
|
||||
|
||||
public byte[] RAM { get; } = new byte[64];
|
||||
|
||||
public Domain[] Domains { get; } = new[]
|
||||
{
|
||||
new Domain(),
|
||||
|
|
@ -50,29 +40,16 @@ namespace DotN64.RCP
|
|||
{
|
||||
MemoryMaps = new[]
|
||||
{
|
||||
new MappingEntry(0x1FC00000, 0x1FC007BF) // PIF Boot ROM.
|
||||
{
|
||||
Read = o => (uint)IPAddress.NetworkToHostOrder(BitConverter.ToInt32(BootROM, (int)o))
|
||||
},
|
||||
new MappingEntry(0x1FC007C0, 0x1FC007FF) // PIF (JoyChannel) RAM.
|
||||
{
|
||||
Read = o => BitConverter.ToUInt32(RAM, (int)o),
|
||||
Write = (o, v) =>
|
||||
{
|
||||
BitHelper.Write(RAM, (int)o, v);
|
||||
|
||||
if (o == CICStatusOffset && RAM[o] == (byte)CICStatus.Waiting) // The boot ROM waits for the PIF's CIC check to be OK.
|
||||
RAM[o] = (byte)CICStatus.OK; // We tell it it's OK by having the loaded word that gets ANDI'd match the immediate value 128, storing non-zero which allows us to exit the BEQL loop.
|
||||
}
|
||||
},
|
||||
new MappingEntry(0x04600010, 0x04600013) // PI status.
|
||||
{
|
||||
Read = o => (uint)Status,
|
||||
Write = (o, v) =>
|
||||
{
|
||||
if ((v & ResetControllerStatus) != 0) { /* TODO. */ }
|
||||
var status = (WriteStatusRegister)v;
|
||||
|
||||
if ((v & ClearInterruptStatus) != 0) { /* TODO. */ }
|
||||
if ((status & WriteStatusRegister.ResetController) != 0) { /* TODO. */ }
|
||||
|
||||
if ((status & WriteStatusRegister.ClearInterrupt) != 0) { /* TODO. */ }
|
||||
}
|
||||
},
|
||||
new MappingEntry(0x04600014, 0x04600017) // PI dom1 latency.
|
||||
|
|
@ -118,61 +95,11 @@ namespace DotN64.RCP
|
|||
},
|
||||
new MappingEntry(0x10000000, 0x1FBFFFFF) // Cartridge Domain 1 Address 2.
|
||||
{
|
||||
Read = o => (uint)IPAddress.NetworkToHostOrder(BitConverter.ToInt32(rcp.Nintendo64.Cartridge.ROM, (int)o))
|
||||
Read = o => BitHelper.FromBigEndian(BitConverter.ToUInt32(rcp.Nintendo64.Cartridge.ROM, (int)o))
|
||||
}
|
||||
};
|
||||
}
|
||||
#endregion
|
||||
|
||||
#region Methods
|
||||
public void EmulateBootROM()
|
||||
{
|
||||
// Replicating the memory writes to properly initialise the subsystems.
|
||||
var writes = new uint[,]
|
||||
{
|
||||
{ 0x4040010, 0xA },
|
||||
{ 0x4600010, 0x3 },
|
||||
{ 0x440000C, 0x3FF },
|
||||
{ 0x4400024, 0x0 },
|
||||
{ 0x4400010, 0x0 },
|
||||
{ 0x4500000, 0x0 },
|
||||
{ 0x4500004, 0x0 },
|
||||
{ 0x4600014, 0x40 }, // These four are likely cartridge-specific (PI domain 1 values).
|
||||
{ 0x4600018, 0xFF803712 },
|
||||
{ 0x460001C, 0xFFFF8037 },
|
||||
{ 0x4600020, 0xFFFFF803 },
|
||||
// Omitted the CIC results.
|
||||
{ 0x1FC007FC, 0xC0 }
|
||||
};
|
||||
|
||||
for (int i = 0; i < writes.GetLength(0); i++)
|
||||
{
|
||||
var address = (ulong)writes[i, 0];
|
||||
|
||||
rcp.Nintendo64.MemoryMaps.WriteWord(address, writes[i, 1]);
|
||||
}
|
||||
|
||||
for (int i = 0x40; i < 0x1000; i += sizeof(uint)) // Copying the bootstrap code from the cartridge to the RSP's DMEM.
|
||||
{
|
||||
var address = (ulong)(0x04000000 + i);
|
||||
|
||||
rcp.Nintendo64.MemoryMaps.WriteWord(address, (uint)IPAddress.NetworkToHostOrder(BitConverter.ToInt32(rcp.Nintendo64.Cartridge.ROM, i)));
|
||||
}
|
||||
|
||||
// Restoring CPU state.
|
||||
rcp.Nintendo64.CPU.CP0.Registers[12] = 0x34000000;
|
||||
rcp.Nintendo64.CPU.CP0.Registers[16] = 0x6E463;
|
||||
rcp.Nintendo64.CPU.GPR[6] = 0xFFFFFFFFA4001F0C;
|
||||
rcp.Nintendo64.CPU.GPR[7] = 0xFFFFFFFFA4001F08;
|
||||
rcp.Nintendo64.CPU.GPR[8] = 0xC0;
|
||||
rcp.Nintendo64.CPU.GPR[10] = 0x40;
|
||||
rcp.Nintendo64.CPU.GPR[11] = 0xFFFFFFFFA4000040;
|
||||
rcp.Nintendo64.CPU.GPR[20] = 0x1;
|
||||
rcp.Nintendo64.CPU.GPR[29] = 0xFFFFFFFFA4001FF0;
|
||||
rcp.Nintendo64.CPU.GPR[31] = 0xFFFFFFFFA4001550;
|
||||
rcp.Nintendo64.CPU.PC = 0xFFFFFFFFA4000040;
|
||||
}
|
||||
#endregion
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,15 +0,0 @@
|
|||
namespace DotN64.RCP
|
||||
{
|
||||
public partial class RealityCoprocessor
|
||||
{
|
||||
public partial class RDRAMInterface
|
||||
{
|
||||
public enum RDRAMConfigIndex : byte
|
||||
{
|
||||
Zero,
|
||||
One,
|
||||
Global
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
using System.Runtime.InteropServices;
|
||||
|
||||
namespace DotN64.RCP
|
||||
{
|
||||
public partial class RealityCoprocessor
|
||||
{
|
||||
public partial class RDRAMInterface
|
||||
{
|
||||
[StructLayout(LayoutKind.Sequential)]
|
||||
public struct RDRAMConfigRegister
|
||||
{
|
||||
#region Fields
|
||||
public uint DeviceType;
|
||||
public uint DeviceID;
|
||||
public uint Delay;
|
||||
public uint Mode;
|
||||
public uint RefInterval;
|
||||
public uint RefRow;
|
||||
public uint RasInterval;
|
||||
public uint MinInterval;
|
||||
public uint AddressSelect;
|
||||
public uint DeviceManufacturer;
|
||||
#endregion
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,9 +1,5 @@
|
|||
using System;
|
||||
|
||||
namespace DotN64.RCP
|
||||
namespace DotN64.RCP
|
||||
{
|
||||
using Helpers;
|
||||
|
||||
public partial class RealityCoprocessor
|
||||
{
|
||||
public partial class RDRAMInterface : Interface
|
||||
|
|
@ -16,8 +12,6 @@ namespace DotN64.RCP
|
|||
public ModeRegister Mode { get; set; }
|
||||
|
||||
public RefreshRegister Refresh { get; set; }
|
||||
|
||||
public RDRAMConfigRegister[] RDRAMConfigs { get; } = new RDRAMConfigRegister[Enum.GetNames(typeof(RDRAMConfigIndex)).Length];
|
||||
#endregion
|
||||
|
||||
#region Constructors
|
||||
|
|
@ -47,69 +41,10 @@ namespace DotN64.RCP
|
|||
{
|
||||
Read = a => Refresh,
|
||||
Write = (a, v) => Refresh = v
|
||||
},
|
||||
new MappingEntry(0x00000000, 0x03EFFFFF) // RDRAM memory.
|
||||
{
|
||||
Read = o => BitConverter.ToUInt32(rcp.Nintendo64.RAM, (int)o),
|
||||
Write = (o, v) => BitHelper.Write(rcp.Nintendo64.RAM, (int)o, v)
|
||||
},
|
||||
new MappingEntry(0x03F00000, 0x03FFFFFF) // RDRAM registers.
|
||||
{
|
||||
Read = o =>
|
||||
{
|
||||
if (!GetRDRAMRegisterInfo((uint)o, out var register, out var index))
|
||||
return 0;
|
||||
|
||||
unsafe
|
||||
{
|
||||
fixed (void* pointer = &RDRAMConfigs[index.Value])
|
||||
{
|
||||
return *((uint*)pointer + register / sizeof(uint));
|
||||
}
|
||||
}
|
||||
},
|
||||
Write = (o, v) =>
|
||||
{
|
||||
if (!GetRDRAMRegisterInfo((uint)o, out var register, out var index))
|
||||
return;
|
||||
|
||||
unsafe
|
||||
{
|
||||
fixed (void* pointer = &RDRAMConfigs[index.Value])
|
||||
{
|
||||
*((uint*)pointer + register / sizeof(uint)) = v;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
}
|
||||
#endregion
|
||||
|
||||
#region Methods
|
||||
private bool GetRDRAMRegisterInfo(uint offset, out uint register, out int? index)
|
||||
{
|
||||
register = offset & ((1 << 8) - 1);
|
||||
|
||||
switch (offset >> 8)
|
||||
{
|
||||
case 0x0000:
|
||||
index = (int)RDRAMConfigIndex.Zero;
|
||||
break;
|
||||
case 0x0004:
|
||||
index = (int)RDRAMConfigIndex.One;
|
||||
break;
|
||||
case 0x0800:
|
||||
index = (int)RDRAMConfigIndex.Global;
|
||||
break;
|
||||
default:
|
||||
index = null;
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
#endregion
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,12 @@
|
|||
namespace DotN64
|
||||
{
|
||||
public partial class RDRAM
|
||||
{
|
||||
public enum ConfigIndex : byte
|
||||
{
|
||||
Zero,
|
||||
One,
|
||||
Global
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
using System.Runtime.InteropServices;
|
||||
|
||||
namespace DotN64
|
||||
{
|
||||
public partial class RDRAM
|
||||
{
|
||||
[StructLayout(LayoutKind.Sequential)]
|
||||
public struct ConfigRegister
|
||||
{
|
||||
#region Fields
|
||||
public uint DeviceType;
|
||||
public uint DeviceID;
|
||||
public uint Delay;
|
||||
public uint Mode;
|
||||
public uint RefInterval;
|
||||
public uint RefRow;
|
||||
public uint RasInterval;
|
||||
public uint MinInterval;
|
||||
public uint AddressSelect;
|
||||
public uint DeviceManufacturer;
|
||||
#endregion
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
using System;
|
||||
using System.Collections.Generic;
|
||||
|
||||
namespace DotN64
|
||||
{
|
||||
using Helpers;
|
||||
|
||||
public partial class RDRAM
|
||||
{
|
||||
#region Properties
|
||||
public IReadOnlyList<MappingEntry> MemoryMaps { get; }
|
||||
|
||||
public byte[] Memory { get; }
|
||||
|
||||
public ConfigRegister[] Configs { get; } = new ConfigRegister[Enum.GetNames(typeof(ConfigIndex)).Length];
|
||||
#endregion
|
||||
|
||||
#region Constructors
|
||||
public RDRAM(byte[] memory)
|
||||
{
|
||||
Memory = memory;
|
||||
MemoryMaps = new[]
|
||||
{
|
||||
new MappingEntry(0x00000000, 0x03EFFFFF) // RDRAM memory.
|
||||
{
|
||||
Read = o => BitConverter.ToUInt32(Memory, (int)o),
|
||||
Write = (o, v) => BitHelper.Write(Memory, (int)o, v)
|
||||
},
|
||||
new MappingEntry(0x03F00000, 0x03FFFFFF) // RDRAM registers.
|
||||
{
|
||||
Read = o =>
|
||||
{
|
||||
if (!GetRegisterInfo((uint)o, out var register, out var index))
|
||||
return 0;
|
||||
|
||||
unsafe
|
||||
{
|
||||
fixed (void* pointer = &Configs[index.Value])
|
||||
{
|
||||
return *((uint*)pointer + register);
|
||||
}
|
||||
}
|
||||
},
|
||||
Write = (o, v) =>
|
||||
{
|
||||
if (!GetRegisterInfo((uint)o, out var register, out var index))
|
||||
return;
|
||||
|
||||
unsafe
|
||||
{
|
||||
fixed (void* pointer = &Configs[index.Value])
|
||||
{
|
||||
*((uint*)pointer + register) = v;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
}
|
||||
#endregion
|
||||
|
||||
#region Methods
|
||||
private bool GetRegisterInfo(uint offset, out uint register, out int? index)
|
||||
{
|
||||
register = (offset & ((1 << 8) - 1)) / sizeof(uint);
|
||||
|
||||
switch (offset >> 8)
|
||||
{
|
||||
case 0x0000:
|
||||
index = (int)ConfigIndex.Zero;
|
||||
break;
|
||||
case 0x0004:
|
||||
index = (int)ConfigIndex.One;
|
||||
break;
|
||||
case 0x0800:
|
||||
index = (int)ConfigIndex.Global;
|
||||
break;
|
||||
default:
|
||||
index = null;
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
#endregion
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue