Replaced CP0 register index abstract property by a readonly field.
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c15c1d0b18
commit
a7972ebc0a
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@ -24,8 +24,6 @@ namespace DotN64.CPU
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#endregion
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#region Properties
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protected override RegisterIndex Index => RegisterIndex.Cause;
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/// <summary>
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/// Exception code field (refer to Table 6-2 for details.)
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/// </summary>
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@ -73,7 +71,7 @@ namespace DotN64.CPU
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#region Constructors
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public CauseRegister(SystemControlUnit cp0)
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: base(cp0) { }
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: base(cp0, RegisterIndex.Cause) { }
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#endregion
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#region Structures
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@ -24,8 +24,6 @@ namespace DotN64.CPU
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#endregion
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#region Properties
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protected override RegisterIndex Index => RegisterIndex.Config;
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/// <summary>
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/// Sets coherency algorithm of kseg0.
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/// </summary>
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@ -74,7 +72,7 @@ namespace DotN64.CPU
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#region Constructors
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public ConfigRegister(SystemControlUnit cp0)
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: base(cp0)
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: base(cp0, RegisterIndex.Config)
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{
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this[constant1] = 0b11001000110;
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this[constant2] = 0b00000110;
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@ -10,6 +10,7 @@ namespace DotN64.CPU
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{
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#region Fields
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private readonly SystemControlUnit cp0;
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private readonly RegisterIndex index;
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#endregion
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#region Properties
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@ -17,11 +18,9 @@ namespace DotN64.CPU
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protected ulong Data
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{
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get => cp0.Registers[(int)Index];
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set => cp0.Registers[(int)Index] = value;
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get => cp0.Registers[(int)index];
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set => cp0.Registers[(int)index] = value;
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}
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protected abstract RegisterIndex Index { get; }
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#endregion
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#region Indexers
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@ -49,9 +48,10 @@ namespace DotN64.CPU
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#endregion
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#region Constructors
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protected Register(SystemControlUnit cp0)
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protected Register(SystemControlUnit cp0, RegisterIndex index)
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{
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this.cp0 = cp0;
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this.index = index;
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}
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#endregion
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}
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@ -29,8 +29,6 @@ namespace DotN64.CPU
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#endregion
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#region Properties
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protected override RegisterIndex Index => RegisterIndex.Status;
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/// <summary>
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/// Specifies and indicates global interrupt enable.
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/// </summary>
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@ -154,7 +152,7 @@ namespace DotN64.CPU
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#region Constructors
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public StatusRegister(SystemControlUnit cp0)
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: base(cp0) { }
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: base(cp0, RegisterIndex.Status) { }
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#endregion
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#region Structures
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