Nabile
/
DotN64
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Added ops.

master
Nabile Rahmani 2018-01-24 16:45:29 +01:00
parent a60f8a7dbf
commit ecab40e39e
6 changed files with 32 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
DotN64/CPU/VR4300/CP0/VR4300.SystemControlUnit.FunctOpCode.cs
View File

@ -7,7 +7,9 @@
public enum FunctOpCode : byte
{
/// <summary>Write Indexed TLB Entry.</summary>
TLBWI = 0b000010
TLBWI = 0b000010,
/// <summary>Return From Exception.</summary>
ERET = 0b011000
}
}
}

20
DotN64/CPU/VR4300/CP0/VR4300.SystemControlUnit.cs
View File

@ -38,13 +38,29 @@ namespace DotN64.CPU
{
if (functOperations.TryGetValue((FunctOpCode)i.Funct, out var operation))
operation(i);
else if (i.Funct == 0b010000)
else //if (i.Funct == 0b010000) // TODO: Uncomment once the operations are implemented.
ExceptionProcessing.ReservedInstruction(cpu, i);
}
};
functOperations = new Dictionary<FunctOpCode, Action<Instruction>>
{
[FunctOpCode.TLBWI] = i => { /* TODO. */ }
[FunctOpCode.TLBWI] = i => { /* TODO. */ },
[FunctOpCode.ERET] = i =>
{
if (Status.ERL)
{
cpu.PC = Registers[(int)RegisterIndex.ErrorEPC];
Status.ERL = false;
}
else
{
cpu.PC = Registers[(int)RegisterIndex.EPC];
Status.EXL = false;
}
cpu.LLBit = false;
cpu.DelaySlot = null;
}
};
}
#endregion

6
DotN64/CPU/VR4300/VR4300.SpecialOpCode.cs
View File

@ -45,7 +45,11 @@
/// <summary>Doubleword Divide Unsigned.</summary>
DDIVU = 0b011111,
/// <summary>Shift Right Arithmetic.</summary>
SRA = 0b000011
SRA = 0b000011,
/// <summary>Move To LO.</summary>
MTLO = 0b010011,
/// <summary>Move To HI.</summary>
MTHI = 0b010001
}
}
}

2
DotN64/CPU/VR4300/VR4300.cs
View File

@ -222,6 +222,8 @@ namespace DotN64.CPU
HI = rs % rt;
},
[Instruction.FromOpCode(SpecialOpCode.SRA)] = i => GPR[i.RD] = (ulong)((int)GPR[i.RT] >> i.SA),
[Instruction.FromOpCode(SpecialOpCode.MTLO)] = i => LO = GPR[i.RS],
[Instruction.FromOpCode(SpecialOpCode.MTHI)] = i => HI = GPR[i.RS],
[Instruction.FromOpCode(RegImmOpCode.BGEZAL)] = i => Branch(i, (rs, rt) => rs >= 0, true),
[Instruction.FromOpCode(RegImmOpCode.BGEZL)] = i => BranchLikely(i, (rs, rt) => rs >= 0)
};

2
DotN64/Diagnostics/Debugger.InstructionFormat.cs
View File

@ -93,6 +93,8 @@
switch (instruction.Special)
{
case VR4300.SpecialOpCode.JR:
case VR4300.SpecialOpCode.MTLO:
case VR4300.SpecialOpCode.MTHI:
return Format(instruction, FormatRegister(instruction.RS, cpu));
case VR4300.SpecialOpCode.MFHI:
case VR4300.SpecialOpCode.MFLO:

2
DotN64/Diagnostics/Debugger.cs
View File

@ -51,6 +51,8 @@ namespace DotN64.Diagnostics
[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.JR)] = InstructionFormat.R,
[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.MFHI)] = InstructionFormat.R,
[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.MFLO)] = InstructionFormat.R,
[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.MTHI)] = InstructionFormat.R,
[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.MTLO)] = InstructionFormat.R,
[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.MULTU)] = InstructionFormat.R,
[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.OR)] = InstructionFormat.R,
[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.SLL)] = InstructionFormat.R,