parent
dbe5cc6559
commit
2ebfa53387
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@ -30,6 +30,8 @@
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BEQ = 0b000100,
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/// <summary>Add Immediate.</summary>
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ADDI = 0b001000,
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/// <summary>Cache Operation.</summary>
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CACHE = 0b101111
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}
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}
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}
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@ -90,7 +90,8 @@ namespace DotN64.CPU
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[OpCode.BNEL] = i => BranchLikely(i, (rs, rt) => rs != rt),
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[OpCode.BNE] = i => Branch(i, (rs, rt) => rs != rt),
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[OpCode.BEQ] = i => Branch(i, (rs, rt) => rs == rt),
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[OpCode.ADDI] = i => GPR[i.RT] = (ulong)(int)(GPR[i.RS] + (ulong)(short)i.Immediate)
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[OpCode.ADDI] = i => GPR[i.RT] = (ulong)(int)(GPR[i.RS] + (ulong)(short)i.Immediate),
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[OpCode.CACHE] = i => { /* TODO: Implement and compare the performance if it's a concern. */ }
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};
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specialOperations = new Dictionary<SpecialOpCode, Action<Instruction>>
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{
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@ -32,6 +32,8 @@ namespace DotN64
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public uint ReadWord(ulong address) => Read(OffsetAddress ? address - StartAddress : address);
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public void WriteWord(ulong address, uint value) => Write(OffsetAddress ? address - StartAddress : address, value);
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public override string ToString() => $"[0x{StartAddress:X16}..0x{EndAddress:X16}] - {(Read != null ? "R" : "-")}{(Write != null ? "W" : "-")}";
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#endregion
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}
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}
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@ -89,6 +89,11 @@ namespace DotN64
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Write = RCP.DP.WriteWord
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},
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new MappingEntry(0x04700000, 0x047FFFFF, false) // RDRAM interface (RI) registers.
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{
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Read = RI.ReadWord,
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Write = RI.WriteWord
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},
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new MappingEntry(0x00000000, 0x03EFFFFF, false) // RDRAM memory.
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{
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Read = RI.ReadWord,
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Write = RI.WriteWord
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@ -1,4 +1,5 @@
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using System.Collections.Generic;
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using System;
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using System.Collections.Generic;
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namespace DotN64.RI
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{
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@ -18,6 +19,8 @@ namespace DotN64.RI
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public ModeRegister Mode { get; set; } = 0x0E;
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public RefreshRegister Refresh { get; set; } = 0x00063634;
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public byte[] RAM { get; } = new byte[0x00400000]; // The base system has 4 MB of RAM installed.
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#endregion
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#region Constructors
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@ -44,6 +47,20 @@ namespace DotN64.RI
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},
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new MappingEntry(0x04700010, 0x04700013) // RI refresh.
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{
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},
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new MappingEntry(0x00000000, 0x03EFFFFF) // RDRAM memory.
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{
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Read = o => BitConverter.ToUInt32(RAM, (int)o),
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Write = (o, v) =>
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{
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unsafe
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{
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fixed (byte* data = &RAM[(int)o])
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{
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*(uint*)data = v;
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}
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}
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}
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}
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};
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}
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