CPU: refactored control flow and load/store methods, added new ops.
parent
dca7725258
commit
eb41337dce
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@ -0,0 +1,13 @@
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namespace DotN64.CPU
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{
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public partial class VR4300
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{
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private enum AccessSize : byte
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{
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Byte,
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HalfWord,
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Word,
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DoubleWord
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}
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}
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}
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@ -55,7 +55,11 @@
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/// <summary>Store Halfword.</summary>
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SH = 0b101001,
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/// <summary>Load Halfword Unsigned.</summary>
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LHU = 0b100101
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LHU = 0b100101,
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/// <summary>Jump.</summary>
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J = 0b000010,
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/// <summary>Load Byte.</summary>
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LB = 0b100000
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}
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}
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}
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@ -7,7 +7,11 @@
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/// <summary>Branch On Greater Than Or Equal To Zero And Link.</summary>
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BGEZAL = 0b10001,
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/// <summary>Branch On Greater Than Or Equal To Zero Likely.</summary>
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BGEZL = 0b00011
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BGEZL = 0b00011,
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/// <summary>Branch On Less Than Zero.</summary>
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BLTZ = 0b00000,
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/// <summary>Branch On Greater Than Or Equal To Zero.</summary>
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BGEZ = 0b00001
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}
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}
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}
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@ -49,7 +49,9 @@
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/// <summary>Move To LO.</summary>
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MTLO = 0b010011,
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/// <summary>Move To HI.</summary>
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MTHI = 0b010001
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MTHI = 0b010001,
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/// <summary>Jump And Link Register.</summary>
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JALR = 0b001001
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}
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}
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}
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@ -135,11 +135,11 @@ namespace DotN64.CPU
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{
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[Instruction.FromOpCode(OpCode.LUI)] = i => GPR[i.RT] = (ulong)(i.Immediate << 16),
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[Instruction.FromOpCode(OpCode.ORI)] = i => GPR[i.RT] = GPR[i.RS] | i.Immediate,
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[Instruction.FromOpCode(OpCode.LW)] = i => GPR[i.RT] = (ulong)(int)ReadWord((ulong)(short)i.Immediate + GPR[i.RS]),
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[Instruction.FromOpCode(OpCode.LW)] = i => Load(i, AccessSize.Word),
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[Instruction.FromOpCode(OpCode.ANDI)] = i => GPR[i.RT] = i.Immediate & GPR[i.RS],
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[Instruction.FromOpCode(OpCode.BEQL)] = i => BranchLikely(i, (rs, rt) => rs == rt),
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[Instruction.FromOpCode(OpCode.ADDIU)] = i => GPR[i.RT] = (ulong)(int)(GPR[i.RS] + (ulong)(short)i.Immediate),
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[Instruction.FromOpCode(OpCode.SW)] = i => WriteWord((ulong)(short)i.Immediate + GPR[i.RS], (uint)GPR[i.RT]),
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[Instruction.FromOpCode(OpCode.SW)] = i => Store(i, AccessSize.Word),
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[Instruction.FromOpCode(OpCode.BNEL)] = i => BranchLikely(i, (rs, rt) => rs != rt),
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[Instruction.FromOpCode(OpCode.BNE)] = i => Branch(i, (rs, rt) => rs != rt),
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[Instruction.FromOpCode(OpCode.BEQ)] = i => Branch(i, (rs, rt) => rs == rt),
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@ -147,41 +147,24 @@ namespace DotN64.CPU
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[Instruction.FromOpCode(OpCode.CACHE)] = i => { /* TODO: Implement and compare the performance if it's a concern. */ },
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[Instruction.FromOpCode(OpCode.JAL)] = i =>
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{
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GPR[31] = PC + Instruction.Size;
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DelaySlot = PC;
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PC = (PC & ~((ulong)(1 << 28) - 1)) | (i.Target << 2);
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StoreLink();
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Jump((PC & ~((ulong)(1 << 28) - 1)) | (i.Target << 2));
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},
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[Instruction.FromOpCode(OpCode.SLTI)] = i => GPR[i.RT] = (long)GPR[i.RS] < (long)(short)i.Immediate ? (ulong)1 : 0,
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[Instruction.FromOpCode(OpCode.XORI)] = i => GPR[i.RT] = GPR[i.RS] ^ i.Immediate,
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[Instruction.FromOpCode(OpCode.BLEZL)] = i => BranchLikely(i, (rs, rt) => rs <= 0),
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[Instruction.FromOpCode(OpCode.SB)] = i =>
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{
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var address = (ulong)(short)i.Immediate + GPR[i.RS];
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WriteWord(address, (ReadWord(address) & ~((uint)(1 << 8) - 1)) | (byte)GPR[i.RT]);
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},
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[Instruction.FromOpCode(OpCode.LBU)] = i => GPR[i.RT] = (byte)ReadWord((ulong)(short)i.Immediate + GPR[i.RS]),
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[Instruction.FromOpCode(OpCode.SB)] = i => Store(i, AccessSize.Byte),
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[Instruction.FromOpCode(OpCode.LBU)] = i => LoadUnsigned(i, AccessSize.Byte),
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[Instruction.FromOpCode(OpCode.COP3)] = i => ExceptionProcessing.ReservedInstruction(this, i), // CP3 access throws a reserved instruction for this CPU.
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[Instruction.FromOpCode(OpCode.BLEZ)] = i => Branch(i, (rs, rt) => rs <= 0),
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[Instruction.FromOpCode(OpCode.LD)] = i =>
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{
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var address = (ulong)(short)i.Immediate + GPR[i.RS];
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GPR[i.RT] = ReadWord(address) << 32 | ReadWord(address + sizeof(uint));
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},
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[Instruction.FromOpCode(OpCode.LD)] = i => Load(i, AccessSize.DoubleWord),
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[Instruction.FromOpCode(OpCode.SLTIU)] = i => GPR[i.RT] = GPR[i.RS] < (ulong)(short)i.Immediate ? (ulong)1 : 0,
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[Instruction.FromOpCode(OpCode.SH)] = i =>
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{
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var address = (ulong)(short)i.Immediate + GPR[i.RS];
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WriteWord(address, (ReadWord(address) & ~((uint)(1 << 16) - 1)) | (ushort)GPR[i.RT]);
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},
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[Instruction.FromOpCode(OpCode.LHU)] = i => GPR[i.RT] = (ushort)ReadWord((ulong)(short)i.Immediate + GPR[i.RS]),
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[Instruction.FromOpCode(OpCode.SH)] = i => Store(i, AccessSize.HalfWord),
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[Instruction.FromOpCode(OpCode.LHU)] = i => LoadUnsigned(i, AccessSize.HalfWord),
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[Instruction.FromOpCode(OpCode.J)] = i => Jump((PC & ~((ulong)(1 << 28) - 1)) | (i.Target << 2)),
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[Instruction.FromOpCode(OpCode.LB)] = i => Load(i, AccessSize.Byte),
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[Instruction.FromOpCode(SpecialOpCode.ADD)] = i => GPR[i.RD] = (ulong)((int)GPR[i.RS] + (int)GPR[i.RT]),
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[Instruction.FromOpCode(SpecialOpCode.JR)] = i =>
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{
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DelaySlot = PC;
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PC = GPR[i.RS];
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},
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[Instruction.FromOpCode(SpecialOpCode.JR)] = i => Jump(GPR[i.RS]),
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[Instruction.FromOpCode(SpecialOpCode.SRL)] = i => GPR[i.RD] = (ulong)((int)GPR[i.RT] >> i.SA),
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[Instruction.FromOpCode(SpecialOpCode.OR)] = i => GPR[i.RD] = GPR[i.RS] | GPR[i.RT],
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[Instruction.FromOpCode(SpecialOpCode.MULTU)] = i =>
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@ -224,8 +207,19 @@ namespace DotN64.CPU
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[Instruction.FromOpCode(SpecialOpCode.SRA)] = i => GPR[i.RD] = (ulong)((int)GPR[i.RT] >> i.SA),
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[Instruction.FromOpCode(SpecialOpCode.MTLO)] = i => LO = GPR[i.RS],
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[Instruction.FromOpCode(SpecialOpCode.MTHI)] = i => HI = GPR[i.RS],
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[Instruction.FromOpCode(RegImmOpCode.BGEZAL)] = i => Branch(i, (rs, rt) => rs >= 0, true),
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[Instruction.FromOpCode(RegImmOpCode.BGEZL)] = i => BranchLikely(i, (rs, rt) => rs >= 0)
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[Instruction.FromOpCode(SpecialOpCode.JALR)] = i =>
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{
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StoreLink((GPRIndex)i.RD);
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Jump(GPR[i.RS]);
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},
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[Instruction.FromOpCode(RegImmOpCode.BGEZAL)] = i =>
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{
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StoreLink();
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Branch(i, (rs, rt) => rs >= 0);
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},
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[Instruction.FromOpCode(RegImmOpCode.BGEZL)] = i => BranchLikely(i, (rs, rt) => rs >= 0),
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[Instruction.FromOpCode(RegImmOpCode.BLTZ)] = i => Branch(i, (rs, rt) => rs < 0),
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[Instruction.FromOpCode(RegImmOpCode.BGEZ)] = i => Branch(i, (rs, rt) => rs >= 0)
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};
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}
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#endregion
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@ -289,18 +283,12 @@ namespace DotN64.CPU
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private bool Branch(Instruction instruction, BranchCondition condition, bool storeLink = false)
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private bool Branch(Instruction instruction, BranchCondition condition)
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{
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var result = condition(GPR[instruction.RS], GPR[instruction.RT]);
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if (storeLink)
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GPR[31] = PC + Instruction.Size;
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if (result)
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{
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DelaySlot = PC;
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PC += (ulong)(short)instruction.Immediate << 2;
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}
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Jump(PC + ((ulong)(short)instruction.Immediate << 2));
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return result;
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}
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@ -313,10 +301,92 @@ namespace DotN64.CPU
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private uint ReadWord(ulong address) => ReadSysAD(CP0.Translate(address));
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private void Jump(ulong address)
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{
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DelaySlot = PC;
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PC = address;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private void WriteWord(ulong address, uint value) => WriteSysAD(CP0.Translate(address), value);
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private void StoreLink(GPRIndex index = GPRIndex.RA) => GPR[(int)index] = PC + Instruction.Size;
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private uint ReadWord(ulong address) => (uint)Read(address, AccessSize.Word);
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private ulong Read(ulong address, AccessSize size)
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{
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var physicalAddress = CP0.Translate(address);
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switch (size)
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{
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case AccessSize.Byte:
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return (byte)ReadSysAD(physicalAddress);
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case AccessSize.HalfWord:
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return (ushort)ReadSysAD(physicalAddress);
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case AccessSize.Word:
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return ReadSysAD(physicalAddress);
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case AccessSize.DoubleWord:
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return ReadSysAD(physicalAddress) << 32 | ReadSysAD(physicalAddress + sizeof(uint));
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default:
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throw new ArgumentException("Invalid system bus access size.", nameof(size));
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}
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private void Write(ulong address, ulong value, AccessSize size)
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{
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var physicalAddress = CP0.Translate(address);
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switch (size)
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{
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case AccessSize.Byte:
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WriteSysAD(physicalAddress, (ReadWord(address) & ~((uint)(1 << 8) - 1)) | (byte)value);
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break;
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case AccessSize.HalfWord:
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WriteSysAD(physicalAddress, (ReadWord(address) & ~((uint)(1 << 16) - 1)) | (ushort)value);
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break;
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case AccessSize.Word:
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WriteSysAD(physicalAddress, (uint)value);
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break;
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case AccessSize.DoubleWord:
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WriteSysAD(physicalAddress, (uint)(value >> 32));
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WriteSysAD(physicalAddress + sizeof(uint), (uint)value);
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break;
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default:
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throw new ArgumentException("Invalid system bus access size.", nameof(size));
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}
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private void Load(Instruction instruction, AccessSize size, bool signExtend = true)
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{
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var value = Read((ulong)(short)instruction.Immediate + GPR[instruction.RS], size);
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if (signExtend)
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{
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switch (size)
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{
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case AccessSize.Byte:
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value = (ulong)(sbyte)value;
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break;
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case AccessSize.HalfWord:
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value = (ulong)(short)value;
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break;
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case AccessSize.Word:
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value = (ulong)(int)value;
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break;
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}
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}
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GPR[instruction.RT] = value;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private void LoadUnsigned(Instruction instruction, AccessSize size) => Load(instruction, size, false);
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private void Store(Instruction instruction, AccessSize size) => Write((ulong)(short)instruction.Immediate + GPR[instruction.RS], GPR[instruction.RT], size);
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#endregion
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}
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}
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@ -67,6 +67,8 @@
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{
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case VR4300.RegImmOpCode.BGEZAL:
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case VR4300.RegImmOpCode.BGEZL:
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case VR4300.RegImmOpCode.BLTZ:
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case VR4300.RegImmOpCode.BGEZ:
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return Format(instruction, FormatRegister(instruction.RS, cpu), (short)instruction.Immediate);
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}
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{
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switch (instruction.Special)
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{
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case VR4300.SpecialOpCode.JALR:
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return Format(instruction, FormatRegister(instruction.RD, cpu), FormatRegister(instruction.RS, cpu));
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case VR4300.SpecialOpCode.JR:
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case VR4300.SpecialOpCode.MTLO:
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case VR4300.SpecialOpCode.MTHI:
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@ -133,7 +137,7 @@
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/// <summary>
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/// Jump type.
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/// </summary>
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public static string J(VR4300.Instruction instruction, VR4300 cpu) => Format(instruction, $"0x{instruction.Target:X8}");
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public static string J(VR4300.Instruction instruction, VR4300 cpu) => Format(instruction, $"0x{((cpu != null ? (cpu.DelaySlot ?? cpu.PC) : 0) & ~(ulong)((1 << 28) - 1)) | (instruction.Target << 2):X8}");
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public static string Unknown(VR4300.Instruction instruction) => FormatOpCode(instruction);
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#endregion
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@ -29,6 +29,7 @@ namespace DotN64.Diagnostics
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.CACHE)] = null,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.COP0)] = InstructionFormat.R, // FIXME: all CP0 ops are treated as such at the moment.
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.JAL)] = InstructionFormat.J,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.J)] = InstructionFormat.J,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.LBU)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.LUI)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.LD)] = InstructionFormat.I,
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@ -41,6 +42,7 @@ namespace DotN64.Diagnostics
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.SLTIU)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.SW)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.XORI)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.LB)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.ADD)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.ADDU)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.AND)] = InstructionFormat.R,
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@ -49,6 +51,7 @@ namespace DotN64.Diagnostics
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.DSLL32)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.DSRA32)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.JR)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.JALR)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.MFHI)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.MFLO)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.MTHI)] = InstructionFormat.R,
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@ -65,7 +68,9 @@ namespace DotN64.Diagnostics
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.SUBU)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.XOR)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.RegImmOpCode.BGEZAL)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.RegImmOpCode.BGEZL)] = InstructionFormat.I
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[VR4300.Instruction.FromOpCode(VR4300.RegImmOpCode.BGEZL)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.RegImmOpCode.BLTZ)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.RegImmOpCode.BGEZ)] = InstructionFormat.I
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};
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#endregion
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@ -92,8 +97,24 @@ namespace DotN64.Diagnostics
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nintendo64.CPU.Cycle();
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}
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}),
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new Command(new[] { "goto", "g" }, "Sets the CPU's PC to the specified address.", args => nintendo64.CPU.PC = ulong.Parse(args.First(), NumberStyles.HexNumber)),
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new Command(new[] { "disassemble", "d" }, "Disassembles instructions from the current PC.", args =>
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new Command(new[] { "goto", "g" }, "Sets the CPU's PC to the specified address or register value.", args =>
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{
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var target = args.First();
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const char RegisterPrefix = '$';
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if (target[0] == RegisterPrefix)
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{
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target = target.Substring(1);
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if (Enum.TryParse<VR4300.GPRIndex>(target, true, out var gprIndex))
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nintendo64.CPU.PC = nintendo64.CPU.GPR[(int)gprIndex];
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else if (Enum.TryParse<VR4300.SystemControlUnit.RegisterIndex>(target, true, out var cp0Index))
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nintendo64.CPU.PC = nintendo64.CPU.CP0.Registers[(int)cp0Index];
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}
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else
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nintendo64.CPU.PC = ulong.Parse(target, NumberStyles.HexNumber);
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}),
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new Command(new[] { "disassemble", "disasm", "d" }, "Disassembles instructions from the current PC.", args =>
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{
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var count = args.Length > 0 ? BigInteger.Parse(args.First()) : 1;
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@ -127,14 +148,14 @@ namespace DotN64.Diagnostics
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{
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foreach (var pair in labels)
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{
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Console.WriteLine($".{pair.Value}: {pair.Key:X16}");
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Console.WriteLine($"{pair.Value}: {pair.Key:X16}");
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}
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break;
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}
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|
||||
var address = ulong.Parse(args[index++], NumberStyles.HexNumber);
|
||||
|
||||
Console.WriteLine($".{labels[address]}: {address:X16}");
|
||||
Console.WriteLine($"{labels[address]}: {address:X16}");
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
|
@ -203,7 +224,7 @@ namespace DotN64.Diagnostics
|
|||
{
|
||||
Console.ForegroundColor = ConsoleColor.Green;
|
||||
|
||||
Console.WriteLine($".{label}:");
|
||||
Console.WriteLine($"{label}:");
|
||||
Console.ResetColor();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -8,6 +8,8 @@
|
|||
<RootNamespace>DotN64</RootNamespace>
|
||||
<AssemblyName>DotN64</AssemblyName>
|
||||
<TargetFrameworkVersion>v4.6.1</TargetFrameworkVersion>
|
||||
<ReleaseVersion>0.0.0.*</ReleaseVersion>
|
||||
<SynchReleaseVersion>false</SynchReleaseVersion>
|
||||
</PropertyGroup>
|
||||
<PropertyGroup Condition=" '$(Configuration)|$(Platform)' == 'Debug|AnyCPU' ">
|
||||
<DebugSymbols>true</DebugSymbols>
|
||||
|
|
@ -93,6 +95,7 @@
|
|||
<Compile Include="CPU\VR4300\CP1\VR4300.FloatingPointUnit.ImplementationRevisionRegister.cs" />
|
||||
<Compile Include="CPU\VR4300\CP1\VR4300.FloatingPointUnit.ControlStatusRegister.cs" />
|
||||
<Compile Include="CPU\VR4300\CP0\VR4300.SystemControlUnit.FunctOpCode.cs" />
|
||||
<Compile Include="CPU\VR4300\VR4300.AccessSize.cs" />
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<Folder Include="CPU\" />
|
||||
|
|
|
|||
Loading…
Reference in New Issue