Instruction: FromOpCode => From.
parent
9762d813ba
commit
a13aa374d3
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@ -127,11 +127,11 @@ namespace DotN64.CPU
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#endregion
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#region Methods
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public static Instruction FromOpCode(OpCode op) => new Instruction { OP = op };
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public static Instruction From(OpCode op) => new Instruction { OP = op };
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public static Instruction FromOpCode(SpecialOpCode op) => new Instruction { Special = op };
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public static Instruction From(SpecialOpCode op) => new Instruction { Special = op };
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public static Instruction FromOpCode(RegImmOpCode op) => new Instruction { RegImm = op };
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public static Instruction From(RegImmOpCode op) => new Instruction { RegImm = op };
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public Instruction ToOpCode()
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@ -134,58 +134,58 @@ namespace DotN64.CPU
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COP[1] = new FloatingPointUnit(this);
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operations = new Dictionary<Instruction, Action<Instruction>>
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{
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[Instruction.FromOpCode(OpCode.LUI)] = i => GPR[i.RT] = (ulong)(i.Immediate << 16),
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[Instruction.FromOpCode(OpCode.ORI)] = i => GPR[i.RT] = GPR[i.RS] | i.Immediate,
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[Instruction.FromOpCode(OpCode.LW)] = i => Load(i, AccessSize.Word),
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[Instruction.FromOpCode(OpCode.ANDI)] = i => GPR[i.RT] = i.Immediate & GPR[i.RS],
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[Instruction.FromOpCode(OpCode.BEQL)] = i => BranchLikely(i, (rs, rt) => rs == rt),
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[Instruction.FromOpCode(OpCode.ADDIU)] = i => GPR[i.RT] = (ulong)(int)(GPR[i.RS] + (ulong)(short)i.Immediate),
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[Instruction.FromOpCode(OpCode.SW)] = i => Store(i, AccessSize.Word),
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[Instruction.FromOpCode(OpCode.BNEL)] = i => BranchLikely(i, (rs, rt) => rs != rt),
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[Instruction.FromOpCode(OpCode.BNE)] = i => Branch(i, (rs, rt) => rs != rt),
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[Instruction.FromOpCode(OpCode.BEQ)] = i => Branch(i, (rs, rt) => rs == rt),
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[Instruction.FromOpCode(OpCode.ADDI)] = i => GPR[i.RT] = (ulong)(int)(GPR[i.RS] + (ulong)(short)i.Immediate),
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[Instruction.FromOpCode(OpCode.CACHE)] = i => { /* TODO: Implement and compare the performance if it's a concern. */ },
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[Instruction.FromOpCode(OpCode.JAL)] = i =>
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[Instruction.From(OpCode.LUI)] = i => GPR[i.RT] = (ulong)(i.Immediate << 16),
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[Instruction.From(OpCode.ORI)] = i => GPR[i.RT] = GPR[i.RS] | i.Immediate,
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[Instruction.From(OpCode.LW)] = i => Load(i, AccessSize.Word),
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[Instruction.From(OpCode.ANDI)] = i => GPR[i.RT] = i.Immediate & GPR[i.RS],
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[Instruction.From(OpCode.BEQL)] = i => BranchLikely(i, (rs, rt) => rs == rt),
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[Instruction.From(OpCode.ADDIU)] = i => GPR[i.RT] = (ulong)(int)(GPR[i.RS] + (ulong)(short)i.Immediate),
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[Instruction.From(OpCode.SW)] = i => Store(i, AccessSize.Word),
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[Instruction.From(OpCode.BNEL)] = i => BranchLikely(i, (rs, rt) => rs != rt),
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[Instruction.From(OpCode.BNE)] = i => Branch(i, (rs, rt) => rs != rt),
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[Instruction.From(OpCode.BEQ)] = i => Branch(i, (rs, rt) => rs == rt),
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[Instruction.From(OpCode.ADDI)] = i => GPR[i.RT] = (ulong)(int)(GPR[i.RS] + (ulong)(short)i.Immediate),
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[Instruction.From(OpCode.CACHE)] = i => { /* TODO: Implement and compare the performance if it's a concern. */ },
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[Instruction.From(OpCode.JAL)] = i =>
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{
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StoreLink();
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Jump((PC & ~((ulong)(1 << 28) - 1)) | (i.Target << 2));
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},
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[Instruction.FromOpCode(OpCode.SLTI)] = i => GPR[i.RT] = (long)GPR[i.RS] < (long)(short)i.Immediate ? (ulong)1 : 0,
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[Instruction.FromOpCode(OpCode.XORI)] = i => GPR[i.RT] = GPR[i.RS] ^ i.Immediate,
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[Instruction.FromOpCode(OpCode.BLEZL)] = i => BranchLikely(i, (rs, rt) => rs <= 0),
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[Instruction.FromOpCode(OpCode.SB)] = i => Store(i, AccessSize.Byte),
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[Instruction.FromOpCode(OpCode.LBU)] = i => LoadUnsigned(i, AccessSize.Byte),
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[Instruction.FromOpCode(OpCode.COP3)] = i => ExceptionProcessing.ReservedInstruction(this, i), // CP3 access throws a reserved instruction for this CPU.
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[Instruction.FromOpCode(OpCode.BLEZ)] = i => Branch(i, (rs, rt) => rs <= 0),
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[Instruction.FromOpCode(OpCode.LD)] = i => Load(i, AccessSize.DoubleWord),
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[Instruction.FromOpCode(OpCode.SLTIU)] = i => GPR[i.RT] = GPR[i.RS] < (ulong)(short)i.Immediate ? (ulong)1 : 0,
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[Instruction.FromOpCode(OpCode.SH)] = i => Store(i, AccessSize.HalfWord),
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[Instruction.FromOpCode(OpCode.LHU)] = i => LoadUnsigned(i, AccessSize.HalfWord),
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[Instruction.FromOpCode(OpCode.J)] = i => Jump((PC & ~((ulong)(1 << 28) - 1)) | (i.Target << 2)),
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[Instruction.FromOpCode(OpCode.LB)] = i => Load(i, AccessSize.Byte),
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[Instruction.FromOpCode(SpecialOpCode.ADD)] = i => GPR[i.RD] = (ulong)((int)GPR[i.RS] + (int)GPR[i.RT]),
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[Instruction.FromOpCode(SpecialOpCode.JR)] = i => Jump(GPR[i.RS]),
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[Instruction.FromOpCode(SpecialOpCode.SRL)] = i => GPR[i.RD] = (ulong)((int)GPR[i.RT] >> i.SA),
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[Instruction.FromOpCode(SpecialOpCode.OR)] = i => GPR[i.RD] = GPR[i.RS] | GPR[i.RT],
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[Instruction.FromOpCode(SpecialOpCode.MULTU)] = i =>
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[Instruction.From(OpCode.SLTI)] = i => GPR[i.RT] = (long)GPR[i.RS] < (long)(short)i.Immediate ? (ulong)1 : 0,
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[Instruction.From(OpCode.XORI)] = i => GPR[i.RT] = GPR[i.RS] ^ i.Immediate,
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[Instruction.From(OpCode.BLEZL)] = i => BranchLikely(i, (rs, rt) => rs <= 0),
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[Instruction.From(OpCode.SB)] = i => Store(i, AccessSize.Byte),
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[Instruction.From(OpCode.LBU)] = i => LoadUnsigned(i, AccessSize.Byte),
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[Instruction.From(OpCode.COP3)] = i => ExceptionProcessing.ReservedInstruction(this, i), // CP3 access throws a reserved instruction for this CPU.
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[Instruction.From(OpCode.BLEZ)] = i => Branch(i, (rs, rt) => rs <= 0),
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[Instruction.From(OpCode.LD)] = i => Load(i, AccessSize.DoubleWord),
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[Instruction.From(OpCode.SLTIU)] = i => GPR[i.RT] = GPR[i.RS] < (ulong)(short)i.Immediate ? (ulong)1 : 0,
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[Instruction.From(OpCode.SH)] = i => Store(i, AccessSize.HalfWord),
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[Instruction.From(OpCode.LHU)] = i => LoadUnsigned(i, AccessSize.HalfWord),
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[Instruction.From(OpCode.J)] = i => Jump((PC & ~((ulong)(1 << 28) - 1)) | (i.Target << 2)),
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[Instruction.From(OpCode.LB)] = i => Load(i, AccessSize.Byte),
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[Instruction.From(SpecialOpCode.ADD)] = i => GPR[i.RD] = (ulong)((int)GPR[i.RS] + (int)GPR[i.RT]),
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[Instruction.From(SpecialOpCode.JR)] = i => Jump(GPR[i.RS]),
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[Instruction.From(SpecialOpCode.SRL)] = i => GPR[i.RD] = (ulong)((int)GPR[i.RT] >> i.SA),
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[Instruction.From(SpecialOpCode.OR)] = i => GPR[i.RD] = GPR[i.RS] | GPR[i.RT],
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[Instruction.From(SpecialOpCode.MULTU)] = i =>
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{
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var result = (ulong)(uint)GPR[i.RS] * (ulong)(uint)GPR[i.RT];
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LO = (ulong)(int)result;
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HI = (ulong)(int)(result >> 32);
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},
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[Instruction.FromOpCode(SpecialOpCode.MFLO)] = i => GPR[i.RD] = LO,
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[Instruction.FromOpCode(SpecialOpCode.SLL)] = i => GPR[i.RD] = (ulong)((int)GPR[i.RT] << i.SA),
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[Instruction.FromOpCode(SpecialOpCode.SUBU)] = i => GPR[i.RD] = (ulong)(int)(GPR[i.RS] - GPR[i.RT]),
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[Instruction.FromOpCode(SpecialOpCode.XOR)] = i => GPR[i.RD] = GPR[i.RS] ^ GPR[i.RT],
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[Instruction.FromOpCode(SpecialOpCode.MFHI)] = i => GPR[i.RD] = HI,
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[Instruction.FromOpCode(SpecialOpCode.ADDU)] = i => GPR[i.RD] = (ulong)((int)GPR[i.RS] + (int)GPR[i.RT]),
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[Instruction.FromOpCode(SpecialOpCode.SLTU)] = i => GPR[i.RD] = (ulong)(GPR[i.RS] < GPR[i.RT] ? 1 : 0),
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[Instruction.FromOpCode(SpecialOpCode.SLLV)] = i => GPR[i.RD] = (ulong)(int)((uint)GPR[i.RT] << (int)(GPR[i.RS] & ((1 << 5) - 1))),
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[Instruction.FromOpCode(SpecialOpCode.SRLV)] = i => GPR[i.RD] = (ulong)(int)((uint)GPR[i.RT] >> (int)(GPR[i.RS] & ((1 << 5) - 1))),
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[Instruction.FromOpCode(SpecialOpCode.AND)] = i => GPR[i.RD] = GPR[i.RS] & GPR[i.RT],
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[Instruction.FromOpCode(SpecialOpCode.SLT)] = i => GPR[i.RD] = (long)GPR[i.RS] < (long)GPR[i.RT] ? (ulong)1 : 0,
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[Instruction.FromOpCode(SpecialOpCode.DMULTU)] = i =>
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[Instruction.From(SpecialOpCode.MFLO)] = i => GPR[i.RD] = LO,
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[Instruction.From(SpecialOpCode.SLL)] = i => GPR[i.RD] = (ulong)((int)GPR[i.RT] << i.SA),
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[Instruction.From(SpecialOpCode.SUBU)] = i => GPR[i.RD] = (ulong)(int)(GPR[i.RS] - GPR[i.RT]),
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[Instruction.From(SpecialOpCode.XOR)] = i => GPR[i.RD] = GPR[i.RS] ^ GPR[i.RT],
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[Instruction.From(SpecialOpCode.MFHI)] = i => GPR[i.RD] = HI,
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[Instruction.From(SpecialOpCode.ADDU)] = i => GPR[i.RD] = (ulong)((int)GPR[i.RS] + (int)GPR[i.RT]),
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[Instruction.From(SpecialOpCode.SLTU)] = i => GPR[i.RD] = (ulong)(GPR[i.RS] < GPR[i.RT] ? 1 : 0),
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[Instruction.From(SpecialOpCode.SLLV)] = i => GPR[i.RD] = (ulong)(int)((uint)GPR[i.RT] << (int)(GPR[i.RS] & ((1 << 5) - 1))),
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[Instruction.From(SpecialOpCode.SRLV)] = i => GPR[i.RD] = (ulong)(int)((uint)GPR[i.RT] >> (int)(GPR[i.RS] & ((1 << 5) - 1))),
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[Instruction.From(SpecialOpCode.AND)] = i => GPR[i.RD] = GPR[i.RS] & GPR[i.RT],
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[Instruction.From(SpecialOpCode.SLT)] = i => GPR[i.RD] = (long)GPR[i.RS] < (long)GPR[i.RT] ? (ulong)1 : 0,
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[Instruction.From(SpecialOpCode.DMULTU)] = i =>
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{
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ulong rsHi = (uint)(GPR[i.RS] >> 32), rtHi = (uint)(GPR[i.RT] >> 32);
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ulong rsLo = (uint)GPR[i.RS], rtLo = (uint)GPR[i.RT];
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@ -193,9 +193,9 @@ namespace DotN64.CPU
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LO = (uint)loProduct + (midProducts << 32);
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HI = hiProduct + (midProducts >> 32);
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},
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[Instruction.FromOpCode(SpecialOpCode.DSLL32)] = i => GPR[i.RD] = GPR[i.RT] << (i.SA + 32),
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[Instruction.FromOpCode(SpecialOpCode.DSRA32)] = i => GPR[i.RD] = (ulong)((long)GPR[i.RT] >> (i.SA + 32)),
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[Instruction.FromOpCode(SpecialOpCode.DDIVU)] = i =>
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[Instruction.From(SpecialOpCode.DSLL32)] = i => GPR[i.RD] = GPR[i.RT] << (i.SA + 32),
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[Instruction.From(SpecialOpCode.DSRA32)] = i => GPR[i.RD] = (ulong)((long)GPR[i.RT] >> (i.SA + 32)),
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[Instruction.From(SpecialOpCode.DDIVU)] = i =>
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{
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ulong rs = GPR[i.RS], rt = GPR[i.RT];
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@ -205,22 +205,22 @@ namespace DotN64.CPU
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LO = rs / rt;
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HI = rs % rt;
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},
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[Instruction.FromOpCode(SpecialOpCode.SRA)] = i => GPR[i.RD] = (ulong)((int)GPR[i.RT] >> i.SA),
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[Instruction.FromOpCode(SpecialOpCode.MTLO)] = i => LO = GPR[i.RS],
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[Instruction.FromOpCode(SpecialOpCode.MTHI)] = i => HI = GPR[i.RS],
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[Instruction.FromOpCode(SpecialOpCode.JALR)] = i =>
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[Instruction.From(SpecialOpCode.SRA)] = i => GPR[i.RD] = (ulong)((int)GPR[i.RT] >> i.SA),
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[Instruction.From(SpecialOpCode.MTLO)] = i => LO = GPR[i.RS],
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[Instruction.From(SpecialOpCode.MTHI)] = i => HI = GPR[i.RS],
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[Instruction.From(SpecialOpCode.JALR)] = i =>
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{
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StoreLink((GPRIndex)i.RD);
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Jump(GPR[i.RS]);
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},
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[Instruction.FromOpCode(RegImmOpCode.BGEZAL)] = i =>
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[Instruction.From(RegImmOpCode.BGEZAL)] = i =>
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{
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StoreLink();
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Branch(i, (rs, rt) => rs >= 0);
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},
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[Instruction.FromOpCode(RegImmOpCode.BGEZL)] = i => BranchLikely(i, (rs, rt) => rs >= 0),
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[Instruction.FromOpCode(RegImmOpCode.BLTZ)] = i => Branch(i, (rs, rt) => rs < 0),
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[Instruction.FromOpCode(RegImmOpCode.BGEZ)] = i => Branch(i, (rs, rt) => rs >= 0)
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[Instruction.From(RegImmOpCode.BGEZL)] = i => BranchLikely(i, (rs, rt) => rs >= 0),
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[Instruction.From(RegImmOpCode.BLTZ)] = i => Branch(i, (rs, rt) => rs < 0),
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[Instruction.From(RegImmOpCode.BGEZ)] = i => Branch(i, (rs, rt) => rs >= 0)
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};
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}
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#endregion
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@ -17,60 +17,60 @@ namespace DotN64.Diagnostics
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private readonly IList<ulong> breakpoints = new List<ulong>();
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private readonly IDictionary<VR4300.Instruction, Func<VR4300.Instruction, VR4300, string>> operationFormats = new Dictionary<VR4300.Instruction, Func<VR4300.Instruction, VR4300, string>>
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{
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.ADDI)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.ADDIU)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.ANDI)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.BEQ)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.BEQL)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.BLEZL)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.BLEZ)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.BNE)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.BNEL)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.CACHE)] = null,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.COP0)] = InstructionFormat.R, // FIXME: all CP0 ops are treated as such at the moment.
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.JAL)] = InstructionFormat.J,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.J)] = InstructionFormat.J,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.LBU)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.LUI)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.LD)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.LHU)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.LW)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.ORI)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.SB)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.SH)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.SLTI)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.SLTIU)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.SW)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.XORI)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.OpCode.LB)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.ADD)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.ADDU)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.AND)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.DDIVU)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.DMULTU)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.DSLL32)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.DSRA32)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.JR)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.JALR)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.MFHI)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.MFLO)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.MTHI)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.MTLO)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.MULTU)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.OR)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.SLL)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.SLLV)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.SLT)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.SLTU)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.SRA)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.SRL)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.SRLV)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.SUBU)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.SpecialOpCode.XOR)] = InstructionFormat.R,
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[VR4300.Instruction.FromOpCode(VR4300.RegImmOpCode.BGEZAL)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.RegImmOpCode.BGEZL)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.RegImmOpCode.BLTZ)] = InstructionFormat.I,
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[VR4300.Instruction.FromOpCode(VR4300.RegImmOpCode.BGEZ)] = InstructionFormat.I
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[VR4300.Instruction.From(VR4300.OpCode.ADDI)] = InstructionFormat.I,
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[VR4300.Instruction.From(VR4300.OpCode.ADDIU)] = InstructionFormat.I,
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[VR4300.Instruction.From(VR4300.OpCode.ANDI)] = InstructionFormat.I,
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[VR4300.Instruction.From(VR4300.OpCode.BEQ)] = InstructionFormat.I,
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[VR4300.Instruction.From(VR4300.OpCode.BEQL)] = InstructionFormat.I,
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[VR4300.Instruction.From(VR4300.OpCode.BLEZL)] = InstructionFormat.I,
|
||||
[VR4300.Instruction.From(VR4300.OpCode.BLEZ)] = InstructionFormat.I,
|
||||
[VR4300.Instruction.From(VR4300.OpCode.BNE)] = InstructionFormat.I,
|
||||
[VR4300.Instruction.From(VR4300.OpCode.BNEL)] = InstructionFormat.I,
|
||||
[VR4300.Instruction.From(VR4300.OpCode.CACHE)] = null,
|
||||
[VR4300.Instruction.From(VR4300.OpCode.COP0)] = InstructionFormat.R, // FIXME: all CP0 ops are treated as such at the moment.
|
||||
[VR4300.Instruction.From(VR4300.OpCode.JAL)] = InstructionFormat.J,
|
||||
[VR4300.Instruction.From(VR4300.OpCode.J)] = InstructionFormat.J,
|
||||
[VR4300.Instruction.From(VR4300.OpCode.LBU)] = InstructionFormat.I,
|
||||
[VR4300.Instruction.From(VR4300.OpCode.LUI)] = InstructionFormat.I,
|
||||
[VR4300.Instruction.From(VR4300.OpCode.LD)] = InstructionFormat.I,
|
||||
[VR4300.Instruction.From(VR4300.OpCode.LHU)] = InstructionFormat.I,
|
||||
[VR4300.Instruction.From(VR4300.OpCode.LW)] = InstructionFormat.I,
|
||||
[VR4300.Instruction.From(VR4300.OpCode.ORI)] = InstructionFormat.I,
|
||||
[VR4300.Instruction.From(VR4300.OpCode.SB)] = InstructionFormat.I,
|
||||
[VR4300.Instruction.From(VR4300.OpCode.SH)] = InstructionFormat.I,
|
||||
[VR4300.Instruction.From(VR4300.OpCode.SLTI)] = InstructionFormat.I,
|
||||
[VR4300.Instruction.From(VR4300.OpCode.SLTIU)] = InstructionFormat.I,
|
||||
[VR4300.Instruction.From(VR4300.OpCode.SW)] = InstructionFormat.I,
|
||||
[VR4300.Instruction.From(VR4300.OpCode.XORI)] = InstructionFormat.I,
|
||||
[VR4300.Instruction.From(VR4300.OpCode.LB)] = InstructionFormat.I,
|
||||
[VR4300.Instruction.From(VR4300.SpecialOpCode.ADD)] = InstructionFormat.R,
|
||||
[VR4300.Instruction.From(VR4300.SpecialOpCode.ADDU)] = InstructionFormat.R,
|
||||
[VR4300.Instruction.From(VR4300.SpecialOpCode.AND)] = InstructionFormat.R,
|
||||
[VR4300.Instruction.From(VR4300.SpecialOpCode.DDIVU)] = InstructionFormat.R,
|
||||
[VR4300.Instruction.From(VR4300.SpecialOpCode.DMULTU)] = InstructionFormat.R,
|
||||
[VR4300.Instruction.From(VR4300.SpecialOpCode.DSLL32)] = InstructionFormat.R,
|
||||
[VR4300.Instruction.From(VR4300.SpecialOpCode.DSRA32)] = InstructionFormat.R,
|
||||
[VR4300.Instruction.From(VR4300.SpecialOpCode.JR)] = InstructionFormat.R,
|
||||
[VR4300.Instruction.From(VR4300.SpecialOpCode.JALR)] = InstructionFormat.R,
|
||||
[VR4300.Instruction.From(VR4300.SpecialOpCode.MFHI)] = InstructionFormat.R,
|
||||
[VR4300.Instruction.From(VR4300.SpecialOpCode.MFLO)] = InstructionFormat.R,
|
||||
[VR4300.Instruction.From(VR4300.SpecialOpCode.MTHI)] = InstructionFormat.R,
|
||||
[VR4300.Instruction.From(VR4300.SpecialOpCode.MTLO)] = InstructionFormat.R,
|
||||
[VR4300.Instruction.From(VR4300.SpecialOpCode.MULTU)] = InstructionFormat.R,
|
||||
[VR4300.Instruction.From(VR4300.SpecialOpCode.OR)] = InstructionFormat.R,
|
||||
[VR4300.Instruction.From(VR4300.SpecialOpCode.SLL)] = InstructionFormat.R,
|
||||
[VR4300.Instruction.From(VR4300.SpecialOpCode.SLLV)] = InstructionFormat.R,
|
||||
[VR4300.Instruction.From(VR4300.SpecialOpCode.SLT)] = InstructionFormat.R,
|
||||
[VR4300.Instruction.From(VR4300.SpecialOpCode.SLTU)] = InstructionFormat.R,
|
||||
[VR4300.Instruction.From(VR4300.SpecialOpCode.SRA)] = InstructionFormat.R,
|
||||
[VR4300.Instruction.From(VR4300.SpecialOpCode.SRL)] = InstructionFormat.R,
|
||||
[VR4300.Instruction.From(VR4300.SpecialOpCode.SRLV)] = InstructionFormat.R,
|
||||
[VR4300.Instruction.From(VR4300.SpecialOpCode.SUBU)] = InstructionFormat.R,
|
||||
[VR4300.Instruction.From(VR4300.SpecialOpCode.XOR)] = InstructionFormat.R,
|
||||
[VR4300.Instruction.From(VR4300.RegImmOpCode.BGEZAL)] = InstructionFormat.I,
|
||||
[VR4300.Instruction.From(VR4300.RegImmOpCode.BGEZL)] = InstructionFormat.I,
|
||||
[VR4300.Instruction.From(VR4300.RegImmOpCode.BLTZ)] = InstructionFormat.I,
|
||||
[VR4300.Instruction.From(VR4300.RegImmOpCode.BGEZ)] = InstructionFormat.I
|
||||
};
|
||||
#endregion
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue