412 lines
17 KiB
C#
412 lines
17 KiB
C#
using System;
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using System.Collections.Generic;
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using System.Runtime.CompilerServices;
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namespace DotN64.CPU
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{
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/// <summary>
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/// The NEC VR4300 CPU, designed by MIPS Technologies.
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/// Datasheet: http://datasheets.chipdb.org/NEC/Vr-Series/Vr43xx/U10504EJ7V0UMJ1.pdf
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/// </summary>
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public partial class VR4300
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{
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#region Fields
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private bool branchDelay;
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private readonly IReadOnlyDictionary<Instruction, Action<Instruction>> operations;
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private readonly IReadOnlyDictionary<byte, float> divModeMultipliers = new Dictionary<byte, float>
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{
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[0b01] = 1.5f,
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[0b10] = 2.0f,
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[0b11] = 3.0f
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};
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private delegate bool BranchCondition(long rs, long rt);
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#endregion
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#region Properties
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/// <summary>
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/// 32 64-bit general purpose registers.
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/// </summary>
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public ulong[] GPR { get; } = new ulong[32];
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/// <summary>
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/// 32 64-bit floating-point operation registers.
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/// </summary>
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public double[] FPR { get; } = new double[32];
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/// <summary>
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/// 64-bit Program Counter.
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/// </summary>
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public ulong PC { get; set; }
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/// <summary>
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/// 64-bit HI register, containing the integer multiply and divide high-order doubleword result.
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/// </summary>
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public ulong HI { get; set; }
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/// <summary>
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/// 64-bit LO register, containing the integer multiply and divide low-order doubleword result.
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/// </summary>
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public ulong LO { get; set; }
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/// <summary>
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/// 1-bit Load/Link LLBit register.
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/// </summary>
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public bool LLBit { get; set; }
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/// <summary>
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/// 32-bit floating-point Implementation/Revision register.
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/// </summary>
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public uint FCR0 { get; set; }
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/// <summary>
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/// 32-bit floating-point Control/Status register.
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/// </summary>
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public uint FCR31 { get; set; }
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private byte divMode;
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/// <summary>
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/// Internal operating frequency mode.
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/// See: datasheet#2.2.2 Table 2-2.
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/// </summary>
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public byte DivMode
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{
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get => divMode;
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set => divMode = (byte)(value & ((1 << 2) - 1));
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}
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public double MasterClock { get; set; }
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/// <summary>
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/// Pipeline clock.
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/// </summary>
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private double PClock => MasterClock * divModeMultipliers[DivMode] * (CP0.Status.RP ? 0.25 : 1.0);
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/// <summary>
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/// System interface clock.
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/// </summary>
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private double SClock => PClock / divModeMultipliers[DivMode];
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/// <summary>
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/// Transmit/receive clock.
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/// </summary>
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public double TClock => SClock;
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private double TicksPerCycle => 1.0 / PClock * TimeSpan.TicksPerSecond;
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/// <summary>
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/// Interrupt request acknowledge.
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/// </summary>
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public byte Int
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{
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get => CP0.Cause.IP.ExternalNormalInterrupts;
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set
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{
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var ip = CP0.Cause.IP;
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ip.ExternalNormalInterrupts = value;
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CP0.Cause.IP = ip;
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}
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}
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/// <summary>
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/// System address/data bus.
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/// </summary>
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public Func<uint, uint> ReadSysAD { get; set; }
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/// <summary>
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/// System address/data bus.
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/// </summary>
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public Action<uint, uint> WriteSysAD { get; set; }
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public ICoprocessor[] COP { get; } = new ICoprocessor[4];
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public SystemControlUnit CP0 => COP[0] as SystemControlUnit;
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public FloatingPointUnit CP1 => COP[1] as FloatingPointUnit;
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public ulong? DelaySlot { get; private set; }
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#endregion
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#region Constructors
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public VR4300()
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{
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COP[0] = new SystemControlUnit(this);
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COP[1] = new FloatingPointUnit(this);
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operations = new Dictionary<Instruction, Action<Instruction>>
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{
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[Instruction.From(OpCode.LUI)] = i => GPR[i.RT] = (ulong)(i.Immediate << 16),
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[Instruction.From(OpCode.ORI)] = i => GPR[i.RT] = GPR[i.RS] | i.Immediate,
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[Instruction.From(OpCode.LW)] = i => Load(i, AccessSize.Word),
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[Instruction.From(OpCode.ANDI)] = i => GPR[i.RT] = i.Immediate & GPR[i.RS],
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[Instruction.From(OpCode.BEQL)] = i => BranchLikely(i, (rs, rt) => rs == rt),
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[Instruction.From(OpCode.ADDIU)] = i => GPR[i.RT] = (ulong)(int)(GPR[i.RS] + (ulong)(short)i.Immediate),
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[Instruction.From(OpCode.SW)] = i => Store(i, AccessSize.Word),
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[Instruction.From(OpCode.BNEL)] = i => BranchLikely(i, (rs, rt) => rs != rt),
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[Instruction.From(OpCode.BNE)] = i => Branch(i, (rs, rt) => rs != rt),
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[Instruction.From(OpCode.BEQ)] = i => Branch(i, (rs, rt) => rs == rt),
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[Instruction.From(OpCode.ADDI)] = i => GPR[i.RT] = (ulong)(int)(GPR[i.RS] + (ulong)(short)i.Immediate),
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[Instruction.From(OpCode.CACHE)] = i => { /* TODO: Implement and compare the performance if it's a concern. */ },
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[Instruction.From(OpCode.JAL)] = i =>
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{
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StoreLink();
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Jump((PC & ~((ulong)(1 << 28) - 1)) | (i.Target << 2));
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},
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[Instruction.From(OpCode.SLTI)] = i => GPR[i.RT] = (long)GPR[i.RS] < (long)(short)i.Immediate ? (ulong)1 : 0,
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[Instruction.From(OpCode.XORI)] = i => GPR[i.RT] = GPR[i.RS] ^ i.Immediate,
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[Instruction.From(OpCode.BLEZL)] = i => BranchLikely(i, (rs, rt) => rs <= 0),
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[Instruction.From(OpCode.SB)] = i => Store(i, AccessSize.Byte),
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[Instruction.From(OpCode.LBU)] = i => LoadUnsigned(i, AccessSize.Byte),
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[Instruction.From(OpCode.COP3)] = i => ExceptionProcessing.ReservedInstruction(this, i), // CP3 access throws a reserved instruction for this CPU.
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[Instruction.From(OpCode.BLEZ)] = i => Branch(i, (rs, rt) => rs <= 0),
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[Instruction.From(OpCode.LD)] = i => Load(i, AccessSize.DoubleWord),
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[Instruction.From(OpCode.SLTIU)] = i => GPR[i.RT] = GPR[i.RS] < (ulong)(short)i.Immediate ? (ulong)1 : 0,
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[Instruction.From(OpCode.SH)] = i => Store(i, AccessSize.HalfWord),
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[Instruction.From(OpCode.LHU)] = i => LoadUnsigned(i, AccessSize.HalfWord),
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[Instruction.From(OpCode.J)] = i => Jump((PC & ~((ulong)(1 << 28) - 1)) | (i.Target << 2)),
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[Instruction.From(OpCode.LB)] = i => Load(i, AccessSize.Byte),
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[Instruction.From(OpCode.BGTZ)] = i => Branch(i, (rs, rt) => rs > 0),
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[Instruction.From(OpCode.SD)] = i => Store(i, AccessSize.DoubleWord),
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[Instruction.From(OpCode.LH)] = i => Load(i, AccessSize.HalfWord),
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[Instruction.From(SpecialOpCode.ADD)] = i => GPR[i.RD] = (ulong)((int)GPR[i.RS] + (int)GPR[i.RT]),
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[Instruction.From(SpecialOpCode.JR)] = i => Jump(GPR[i.RS]),
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[Instruction.From(SpecialOpCode.SRL)] = i => GPR[i.RD] = (ulong)(int)((uint)GPR[i.RT] >> i.SA),
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[Instruction.From(SpecialOpCode.OR)] = i => GPR[i.RD] = GPR[i.RS] | GPR[i.RT],
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[Instruction.From(SpecialOpCode.MULTU)] = i =>
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{
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var result = (ulong)(uint)GPR[i.RS] * (ulong)(uint)GPR[i.RT];
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LO = (ulong)(int)result;
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HI = (ulong)(int)(result >> 32);
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},
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[Instruction.From(SpecialOpCode.MFLO)] = i => GPR[i.RD] = LO,
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[Instruction.From(SpecialOpCode.SLL)] = i => GPR[i.RD] = (ulong)((int)GPR[i.RT] << i.SA),
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[Instruction.From(SpecialOpCode.SUBU)] = i => GPR[i.RD] = (ulong)(int)(GPR[i.RS] - GPR[i.RT]),
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[Instruction.From(SpecialOpCode.XOR)] = i => GPR[i.RD] = GPR[i.RS] ^ GPR[i.RT],
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[Instruction.From(SpecialOpCode.MFHI)] = i => GPR[i.RD] = HI,
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[Instruction.From(SpecialOpCode.ADDU)] = i => GPR[i.RD] = (ulong)((int)GPR[i.RS] + (int)GPR[i.RT]),
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[Instruction.From(SpecialOpCode.SLTU)] = i => GPR[i.RD] = (ulong)(GPR[i.RS] < GPR[i.RT] ? 1 : 0),
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[Instruction.From(SpecialOpCode.SLLV)] = i => GPR[i.RD] = (ulong)(int)((uint)GPR[i.RT] << (int)(GPR[i.RS] & ((1 << 5) - 1))),
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[Instruction.From(SpecialOpCode.SRLV)] = i => GPR[i.RD] = (ulong)(int)((uint)GPR[i.RT] >> (int)(GPR[i.RS] & ((1 << 5) - 1))),
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[Instruction.From(SpecialOpCode.AND)] = i => GPR[i.RD] = GPR[i.RS] & GPR[i.RT],
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[Instruction.From(SpecialOpCode.SLT)] = i => GPR[i.RD] = (long)GPR[i.RS] < (long)GPR[i.RT] ? (ulong)1 : 0,
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[Instruction.From(SpecialOpCode.DMULTU)] = i =>
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{
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ulong rsHi = (uint)(GPR[i.RS] >> 32), rtHi = (uint)(GPR[i.RT] >> 32);
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ulong rsLo = (uint)GPR[i.RS], rtLo = (uint)GPR[i.RT];
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ulong midProducts = rsHi * rtLo + rsLo * rtHi, loProduct = rsLo * rtLo, hiProduct = rsHi * rtHi;
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LO = (uint)loProduct + (midProducts << 32);
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HI = hiProduct + (midProducts >> 32);
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},
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[Instruction.From(SpecialOpCode.DSLL32)] = i => GPR[i.RD] = GPR[i.RT] << (i.SA + 32),
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[Instruction.From(SpecialOpCode.DSRA32)] = i => GPR[i.RD] = (ulong)((long)GPR[i.RT] >> (i.SA + 32)),
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[Instruction.From(SpecialOpCode.DDIVU)] = i =>
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{
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ulong rs = GPR[i.RS], rt = GPR[i.RT];
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if (rt == 0)
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return;
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LO = rs / rt;
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HI = rs % rt;
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},
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[Instruction.From(SpecialOpCode.SRA)] = i => GPR[i.RD] = (ulong)((int)GPR[i.RT] >> i.SA),
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[Instruction.From(SpecialOpCode.MTLO)] = i => LO = GPR[i.RS],
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[Instruction.From(SpecialOpCode.MTHI)] = i => HI = GPR[i.RS],
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[Instruction.From(SpecialOpCode.JALR)] = i =>
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{
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StoreLink((GPRIndex)i.RD);
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Jump(GPR[i.RS]);
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},
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[Instruction.From(RegImmOpCode.BGEZAL)] = i =>
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{
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StoreLink();
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Branch(i, (rs, rt) => rs >= 0);
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},
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[Instruction.From(RegImmOpCode.BGEZL)] = i => BranchLikely(i, (rs, rt) => rs >= 0),
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[Instruction.From(RegImmOpCode.BLTZ)] = i => Branch(i, (rs, rt) => rs < 0),
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[Instruction.From(RegImmOpCode.BGEZ)] = i => Branch(i, (rs, rt) => rs >= 0)
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};
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}
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#endregion
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#region Methods
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/// <summary>
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/// Cold reset.
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/// See: datasheet#6.4.4.
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/// </summary>
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public void Reset() => ExceptionProcessing.ColdReset(this);
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public void Run(Instruction instruction)
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{
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if (operations.TryGetValue(instruction.ToOpCode(), out var operation))
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operation(instruction);
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else if (instruction.COPz.HasValue)
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{
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var unit = instruction.COPz.Value;
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if (CP0.IsCoprocessorUsable(unit))
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COP[unit].Run(instruction);
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else
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ExceptionProcessing.CoprocessorUnusable(this, unit);
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}
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else
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ExceptionProcessing.ReservedInstruction(this, instruction);
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GPR[(int)GPRIndex.Zero] = 0;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private void Step()
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{
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Instruction instruction;
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branchDelay = DelaySlot.HasValue;
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if (!branchDelay)
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{
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instruction = ReadWord(PC);
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PC += Instruction.Size;
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}
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else
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{
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instruction = ReadWord(DelaySlot.Value);
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DelaySlot = null;
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}
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Run(instruction);
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public void Cycle()
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{
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CP0.IncrementCounter();
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if (CP0.HasPendingInterrupt)
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{
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ExceptionProcessing.Interrupt(this);
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return;
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}
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Step();
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private bool Branch(Instruction instruction, BranchCondition condition)
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{
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var result = condition((long)GPR[instruction.RS], (long)GPR[instruction.RT]);
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if (result)
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Jump(PC + ((ulong)(short)instruction.Immediate << 2));
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return result;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private void BranchLikely(Instruction instruction, BranchCondition condition)
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{
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if (!Branch(instruction, condition))
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PC += Instruction.Size;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private void Jump(ulong address)
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{
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DelaySlot = PC;
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PC = address;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private void StoreLink(GPRIndex index = GPRIndex.RA) => GPR[(int)index] = PC + Instruction.Size;
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private uint ReadWord(ulong address) => (uint)Read(address, AccessSize.Word);
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private ulong Read(ulong address, AccessSize size)
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{
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var physicalAddress = CP0.Translate(address);
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switch (size)
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{
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case AccessSize.Byte:
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physicalAddress &= ~0b11u;
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return (byte)(ReadSysAD(physicalAddress) >> (((int)address & 0b11 ^ -(int)CP0.Config.BE) << 3));
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case AccessSize.HalfWord:
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physicalAddress &= ~0b11u;
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return (ushort)(ReadSysAD(physicalAddress) >> (((int)address & 0b11 ^ (-(int)CP0.Config.BE << 1)) << 3));
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case AccessSize.Word:
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return ReadSysAD(physicalAddress);
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case AccessSize.DoubleWord:
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return (ulong)ReadSysAD(physicalAddress) << 32 | (ulong)ReadSysAD(physicalAddress + sizeof(uint));
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default:
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throw new ArgumentException("Invalid system bus access size.", nameof(size));
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}
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private void Write(ulong address, ulong data, AccessSize size)
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{
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var physicalAddress = CP0.Translate(address);
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switch (size)
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{
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case AccessSize.Byte:
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{
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physicalAddress &= ~0b11u;
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var shift = ((int)address & 0b11 ^ -(int)CP0.Config.BE) << 3;
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WriteSysAD(physicalAddress, (ReadSysAD(physicalAddress) & ~((uint)byte.MaxValue << shift)) | (uint)((byte)data << shift));
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}
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break;
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case AccessSize.HalfWord:
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{
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physicalAddress &= ~0b11u;
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var shift = ((int)address & 0b11 ^ (-(int)CP0.Config.BE << 1)) << 3;
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WriteSysAD(physicalAddress, (ReadSysAD(physicalAddress) & ~((uint)ushort.MaxValue << shift)) | (uint)((ushort)data << shift));
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}
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break;
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case AccessSize.Word:
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WriteSysAD(physicalAddress, (uint)data);
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break;
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case AccessSize.DoubleWord:
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WriteSysAD(physicalAddress, (uint)(data >> 32));
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WriteSysAD(physicalAddress + sizeof(uint), (uint)data);
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break;
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default:
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throw new ArgumentException("Invalid system bus access size.", nameof(size));
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}
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private void Load(Instruction instruction, AccessSize size, bool signExtend = true)
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{
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var value = Read((ulong)(short)instruction.Immediate + GPR[instruction.RS], size);
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if (signExtend)
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{
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switch (size)
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{
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case AccessSize.Byte:
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value = (ulong)(sbyte)value;
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break;
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case AccessSize.HalfWord:
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value = (ulong)(short)value;
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break;
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case AccessSize.Word:
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value = (ulong)(int)value;
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break;
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}
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}
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GPR[instruction.RT] = value;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private void LoadUnsigned(Instruction instruction, AccessSize size) => Load(instruction, size, false);
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private void Store(Instruction instruction, AccessSize size) => Write((ulong)(short)instruction.Immediate + GPR[instruction.RS], GPR[instruction.RT], size);
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#endregion
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}
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}
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