DotN64/DotN64/CPU/VR4300
Nabile Rahmani a4d06cef67 Handle special cases for CP0 register writes.
- The timer interrupt is cleared on writes to the Compare register (see: #6.3.4).
- Only software interrupt bits are writable into the Cause register (see: #6.3.6).
2018-12-24 21:38:18 +01:00
..
CP0 Handle special cases for CP0 register writes. 2018-12-24 21:38:18 +01:00
CP1 FPU: 2018-06-05 17:19:02 +02:00
VR4300.AccessSize.cs CPU: refactored control flow and load/store methods, added new ops. 2018-06-09 17:40:52 +02:00
VR4300.ExceptionProcessing.cs Inline exception processing methods. 2018-12-11 19:39:32 +01:00
VR4300.Exceptions.cs Coprocessor, debugger, and exception stuff. 2018-01-17 10:34:02 +01:00
VR4300.GPRIndex.cs Changed casing to follow naming conventions. 2017-12-18 09:10:07 +01:00
VR4300.ICoprocessor.cs Coprocessor, debugger, and exception stuff. 2018-01-17 10:34:02 +01:00
VR4300.Instruction.cs Instruction: FromOpCode => From. 2018-06-09 18:56:57 +02:00
VR4300.OpCode.cs Make the CPU SB/SH tests pass. 2018-12-10 19:59:20 +01:00
VR4300.RegImmOpCode.cs CPU: refactored control flow and load/store methods, added new ops. 2018-06-09 17:40:52 +02:00
VR4300.SpecialOpCode.cs CPU: refactored control flow and load/store methods, added new ops. 2018-06-09 17:40:52 +02:00
VR4300.cs Fixed incorrect masking for sub-word writes. 2018-12-19 15:43:20 +01:00