- The timer interrupt is cleared on writes to the Compare register (see: #6.3.4).
- Only software interrupt bits are writable into the Cause register (see: #6.3.6).
- Added an exception handler for the FPU.
- Added constants for cartridges and fixed header properties.
- PIF HLE determines the console region for the saved register that's used by the OS.
- The disassembler shows CP1 opcodes.
* VR4300.SystemControlUnit.cs: Implemented coprocessor operations.
* VR4300.ExceptionProcessing.cs: More exceptions.
* VR4300.Exceptions.cs: Support coprocessor ops.
* DotN64.csproj:
* VR4300.ICoprocessor.cs:
* VR4300.Instruction.cs: Implemented IEquatable to avoid boxing in
dictionary key comparisons.
Added COPz for coprocessor ops.
* VR4300.OpCode.cs: Proper coprocessor ops.
* VR4300.cs: Added coprocessor unit support.
* Debugger.InstructionFormat.cs: (Slightly) take into account
coprocessor ops.
* Debugger.cs: Using an instruction cursor to avoid confusion.
Fixed a case where the debugger would run a cycle despite exiting it.
Coprocessor ops aren't properly disassembled.
* VR4300.SystemControlUnit.StatusRegister.cs: Removed unneeded
value.
* VR4300.SystemControlUnit.cs: Renamed method.
* VR4300.Instruction.cs: Refactored instruction contents. Now
individual parts can be written to as well.
It is also possible to strip an instruction to its bare opcode
identifier, or even create one from a specified opcode, so this can
be used as a key in a dictionary of operations.
A basic ToString implementation displays the opcode of the
instruction.
* VR4300.OpCode.cs:
* VR4300.RegImmOpCode.cs:
* VR4300.SpecialOpCode.cs: Added opcodes.
* VR4300.cs: Unified operations into a single dictionary thanks to the
instruction refactoring.
Added ops: JAL, SLTI, XORI, BLEZL, SB, LBU, SLT, BGEZL.
* Debugger.Command.cs: Basic display of what the command is about.
* Debugger.InstructionFormat.cs: First pass of the formatter.
* Debugger.cs: Proper disassembly of instructions. Stepping also
displays the contents of registers.
~Infinite~ count argument for stepping/disassembling.
Refactored instruction fetch into using the CPU's SysAD bus (no need
to manually access the N64's memory maps).
* DotN64.csproj:
* RealityCoprocessor.SignalProcessor.StatusRegister.cs:
* RealityCoprocessor.DisplayProcessor.StatusRegister.cs:
* RealityCoprocessor.RDRAMInterface.RDRAMConfigIndex.cs:
* RealityCoprocessor.RDRAMInterface.RDRAMConfigRegister.cs:
* MappingEntryExtensions.cs: Saves some typing.
* BitHelper.cs: Reusable methods.
* Nintendo64.cs: More memory maps.
* Program.cs: Minor changes.
* RealityCoprocessor.Interface.cs:
* RealityCoprocessor.AudioInterface.cs:
* RealityCoprocessor.VideoInterface.cs:
* RealityCoprocessor.SerialInterface.cs: Simplified mapping accesses.
* RealityCoprocessor.DisplayProcessor.cs: Added an actual register.
Simplified mapping accesses.
* RealityCoprocessor.MIPSInterface.cs: Added dummy version register
read.
Simplified mapping accesses.
* RealityCoprocessor.PeripheralInterface.cs: Basic DMA.
Simplified mapping accesses.
* RealityCoprocessor.RDRAMInterface.cs: Removed constants that get set
in the boot process.
Added RDRAM registers.
Simplified mapping accesses.
* RealityCoprocessor.SignalProcessor.cs: Better types for existing
registers and handle status writes.
Simplified mapping accesses.
Nabile Rahmani