From dade03d7f7dd6134bc20df03afe67b2633cee1fb Mon Sep 17 00:00:00 2001
From: Nabile Rahmani <nabile13.pc@gmail.com>
Date: Sun, 17 Jun 2018 04:09:29 +0200
Subject: [PATCH] CPUADD wants these.

---
 DotN64/CPU/VR4300/VR4300.OpCode.cs                 | 4 +++-
 DotN64/CPU/VR4300/VR4300.cs                        | 1 +
 DotN64/Diagnostics/Debugger.InstructionFormat.cs   | 1 +
 DotN64/Diagnostics/Debugger.cs                     | 3 ++-
 DotN64/RCP/VI/RealityCoprocessor.VideoInterface.cs | 1 +
 5 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/DotN64/CPU/VR4300/VR4300.OpCode.cs b/DotN64/CPU/VR4300/VR4300.OpCode.cs
index 61cd9aa..7b1f672 100644
--- a/DotN64/CPU/VR4300/VR4300.OpCode.cs
+++ b/DotN64/CPU/VR4300/VR4300.OpCode.cs
@@ -59,7 +59,9 @@
             /// <summary>Jump.</summary>
             J = 0b000010,
             /// <summary>Load Byte.</summary>
-            LB = 0b100000
+            LB = 0b100000,
+            /// <summary>Branch On Greater Than Zero.</summary>
+            BGTZ = 0b000111
         }
     }
 }
diff --git a/DotN64/CPU/VR4300/VR4300.cs b/DotN64/CPU/VR4300/VR4300.cs
index aebd124..719889e 100644
--- a/DotN64/CPU/VR4300/VR4300.cs
+++ b/DotN64/CPU/VR4300/VR4300.cs
@@ -164,6 +164,7 @@ namespace DotN64.CPU
                 [Instruction.From(OpCode.LHU)] = i => LoadUnsigned(i, AccessSize.HalfWord),
                 [Instruction.From(OpCode.J)] = i => Jump((PC & ~((ulong)(1 << 28) - 1)) | (i.Target << 2)),
                 [Instruction.From(OpCode.LB)] = i => Load(i, AccessSize.Byte),
+                [Instruction.From(OpCode.BGTZ)] = i => Branch(i, (rs, rt) => rs > 0),
                 [Instruction.From(SpecialOpCode.ADD)] = i => GPR[i.RD] = (ulong)((int)GPR[i.RS] + (int)GPR[i.RT]),
                 [Instruction.From(SpecialOpCode.JR)] = i => Jump(GPR[i.RS]),
                 [Instruction.From(SpecialOpCode.SRL)] = i => GPR[i.RD] = (ulong)((int)GPR[i.RT] >> i.SA),
diff --git a/DotN64/Diagnostics/Debugger.InstructionFormat.cs b/DotN64/Diagnostics/Debugger.InstructionFormat.cs
index 09e8a96..4746805 100644
--- a/DotN64/Diagnostics/Debugger.InstructionFormat.cs
+++ b/DotN64/Diagnostics/Debugger.InstructionFormat.cs
@@ -81,6 +81,7 @@
                         return Format(instruction, FormatRegister(instruction.RS, cpu), FormatRegister(instruction.RT, cpu), (short)instruction.Immediate);
                     case VR4300.OpCode.BLEZL:
                     case VR4300.OpCode.BLEZ:
+                    case VR4300.OpCode.BGTZ:
                         return Format(instruction, FormatRegister(instruction.RS, cpu), (short)instruction.Immediate);
                     default:
                         return Format(instruction, FormatRegister(instruction.RT, cpu), FormatRegister(instruction.RS, cpu), (short)instruction.Immediate);
diff --git a/DotN64/Diagnostics/Debugger.cs b/DotN64/Diagnostics/Debugger.cs
index 7adbc24..0d0cf8c 100644
--- a/DotN64/Diagnostics/Debugger.cs
+++ b/DotN64/Diagnostics/Debugger.cs
@@ -22,6 +22,7 @@ namespace DotN64.Diagnostics
             [VR4300.Instruction.From(VR4300.OpCode.ANDI)] = InstructionFormat.I,
             [VR4300.Instruction.From(VR4300.OpCode.BEQ)] = InstructionFormat.I,
             [VR4300.Instruction.From(VR4300.OpCode.BEQL)] = InstructionFormat.I,
+            [VR4300.Instruction.From(VR4300.OpCode.BGTZ)] = InstructionFormat.I,
             [VR4300.Instruction.From(VR4300.OpCode.BLEZL)] = InstructionFormat.I,
             [VR4300.Instruction.From(VR4300.OpCode.BLEZ)] = InstructionFormat.I,
             [VR4300.Instruction.From(VR4300.OpCode.BNE)] = InstructionFormat.I,
@@ -30,6 +31,7 @@ namespace DotN64.Diagnostics
             [VR4300.Instruction.From(VR4300.OpCode.COP0)] = InstructionFormat.R, // FIXME: all CP0 ops are treated as such at the moment.
             [VR4300.Instruction.From(VR4300.OpCode.JAL)] = InstructionFormat.J,
             [VR4300.Instruction.From(VR4300.OpCode.J)] = InstructionFormat.J,
+            [VR4300.Instruction.From(VR4300.OpCode.LB)] = InstructionFormat.I,
             [VR4300.Instruction.From(VR4300.OpCode.LBU)] = InstructionFormat.I,
             [VR4300.Instruction.From(VR4300.OpCode.LUI)] = InstructionFormat.I,
             [VR4300.Instruction.From(VR4300.OpCode.LD)] = InstructionFormat.I,
@@ -42,7 +44,6 @@ namespace DotN64.Diagnostics
             [VR4300.Instruction.From(VR4300.OpCode.SLTIU)] = InstructionFormat.I,
             [VR4300.Instruction.From(VR4300.OpCode.SW)] = InstructionFormat.I,
             [VR4300.Instruction.From(VR4300.OpCode.XORI)] = InstructionFormat.I,
-            [VR4300.Instruction.From(VR4300.OpCode.LB)] = InstructionFormat.I,
             [VR4300.Instruction.From(VR4300.SpecialOpCode.ADD)] = InstructionFormat.R,
             [VR4300.Instruction.From(VR4300.SpecialOpCode.ADDU)] = InstructionFormat.R,
             [VR4300.Instruction.From(VR4300.SpecialOpCode.AND)] = InstructionFormat.R,
diff --git a/DotN64/RCP/VI/RealityCoprocessor.VideoInterface.cs b/DotN64/RCP/VI/RealityCoprocessor.VideoInterface.cs
index 64aa809..e2b9fb7 100644
--- a/DotN64/RCP/VI/RealityCoprocessor.VideoInterface.cs
+++ b/DotN64/RCP/VI/RealityCoprocessor.VideoInterface.cs
@@ -77,6 +77,7 @@
                     },
                     new MappingEntry(0x04400010, 0x04400013) // VI current vertical line.
                     {
+                        Read = o => CurrentVerticalLine,
                         Write = (o, d) =>
                         {
                             CurrentVerticalLine = (ushort)(d & ((1 << 10) - 1));